DLL Duty-Cycle Corrector for 50% Clock Signal Accuracy
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Solution Overview
Problem
High-speed circuits face challenges in maintaining a fifty percent duty cycle for clock signals due to variations in process, voltage, and temperature, and existing duty-cycle corrector circuits are complex, power-consuming, and inefficient.
Innovation Solution
The implementation of a duty-cycle corrector circuit using a delay-locked loop (DLL) and duty-cycle correction (DCC) circuit, which adjusts the delay between local clock signals and their inverted versions to align rising edges and correct duty cycles, utilizing a phase detector, charge pump, low-pass filter, and duty adjusting circuits to achieve a fifty percent duty cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an analog integrator is used to detect duty cycle error, then the circuit can detect duty cycle deviations, but it can only be used in low-speed applications
Solution Approach 1:
The patent replaces the analog integrator (mechanical/electrical continuous system) with a digital duty-cycle corrector circuit that uses digital signal processing. The digital circuit includes delay elements, XOR gates, and flip-flops that operate on discrete clock cycles, enabling high-speed operation while maintaining duty cycle detection and correction functionality through digital logic operations instead of continuous analog integration.
2Manufacturing precision
If two delay lines are used to correct duty cycle accuracy, then the duty cycle can be corrected, but the circuit becomes complicated and power consumption increases
Solution Approach 1:
The patent merges the duty cycle detection and correction functions into a single integrated digital circuit block. Instead of separate delay lines for detection and correction, the invention uses a unified structure where the delay element, XOR gate, and flip-flop work together as one cohesive unit that simultaneously detects duty cycle errors and applies corrections, reducing overall circuit complexity.
Solution Approach 2:
The digital duty-cycle corrector circuit performs multiple functions within a single circuit architecture: it detects duty cycle deviations, generates correction signals, and applies corrections to the clock signal. The delay element serves both as a timing reference and as part of the correction mechanism, while the XOR gate simultaneously compares phases and generates error detection signals.
3Measurement precision
If a comparator circuit is used to compare signal levels of two delay lines, then duty cycle accuracy can be determined, but the circuit consumes large area on the die
Solution Approach 1:
The patent extracts the duty cycle measurement function from a complex comparator circuit and implements it using simpler digital logic elements. Instead of using a full comparator that requires multiple transistors and large area, the invention uses XOR gates and flip-flops that can determine duty cycle accuracy with minimal circuitry, taking out only the essential comparison functionality needed for duty cycle measurement.
Data Source
AI summary
A duty-cycle corrector circuit produces a clock signal with a given duty cycle (e.g., fifty percent) or with a substantially given duty cycle. The DC corrector circuit includes a delay-locked loop (DLL) circuit and a duty-cycle correction (DCC) circuit. The DLL circuit is operable to adjust a delay between local clock signals until the phase difference between the local clock signals equals or is substantially equal to zero. The DCC circuit is operable to adjust the duty cycles of the local clock signals until the duty-cycle error equals or is substantially equal to zero. The duty-cycle error equals or substantially equals zero when the duty cycles of the local clock signals equal or are substantially equal to fifty percent.