DLL Duty-Cycle Corrector for High-Speed 50% Clock Signals
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Solution Overview
Problem
High-speed circuits face challenges in maintaining a fifty percent duty cycle for clock signals due to variations in process, voltage, and temperature, and existing duty-cycle corrector circuits are complex, power-consuming, and limited to low-speed applications.
Innovation Solution
A duty-cycle corrector circuit utilizing a delay-locked loop (DLL) and duty-cycle correction (DCC) circuit, which adjusts the delay between local clock signals and their inverted versions to align rising edges and correct duty cycles, achieving a fifty percent duty cycle through a phase detector, charge pump, low-pass filter, and duty adjusting mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an analog integrator is used to detect duty cycle error, then duty cycle correction can be achieved, but the circuit is limited to low-speed applications only
Solution Approach 1:
The patent replaces the analog integrator (mechanical/electrical continuous system) with a digital counter-based detection mechanism. The counter counts clock cycles during high and low periods, converting continuous analog duty cycle detection into discrete digital counting, enabling high-speed operation while maintaining correction capability
Solution Approach 2:
The patent changes the detection parameter from analog voltage integration to digital cycle counting. By counting the number of clock cycles during high and low periods rather than integrating analog signals, the system achieves both high-speed operation and broad application range including both low-speed and high-speed circuits
2Measurement precision
If two delay lines are used to correct duty cycle accuracy, then correction precision is improved, but circuit complexity and power consumption increase
Solution Approach 1:
The patent extracts only the essential correction function from the complex two-delay-line system. By using a single delay line controlled by digitally generated correction pulses based on counter measurements, the system achieves duty cycle accuracy without requiring two separate delay lines and their associated comparator circuits
Solution Approach 2:
The patent discards the redundant components of traditional duty cycle correctors (second delay line, complex comparators) and recovers the essential correction function through a simplified digital control mechanism that generates correction pulses based on counter-measured duty cycle errors
3Measurement precision
If a comparator circuit is used to compare signal levels of two delay lines, then duty cycle correction can be achieved, but the circuit consumes large area and power
Solution Approach 1:
The patent replaces the analog comparator circuit with a digital counter-based detection system. Instead of using continuous analog voltage comparison that consumes power, the system uses digital counting of clock cycles during high and low periods, achieving duty cycle detection with significantly reduced power consumption
Solution Approach 2:
The patent uses simple digital counters and logic gates instead of complex comparator circuits. These digital components are less power-consuming and occupy less area, providing an economical solution that achieves the same duty cycle detection function with reduced resource consumption
Data Source
AI summary
A duty-cycle corrector circuit produces a clock signal with a given duty cycle (e.g., fifty percent) or with a substantially given duty cycle. The DC corrector circuit includes a delay-locked loop (DLL) circuit and a duty-cycle correction (DCC) circuit. The DLL circuit is operable to adjust a delay between local clock signals until the phase difference between the local clock signals equals or is substantially equal to zero. The DCC circuit is operable to adjust the duty cycles of the local clock signals until the duty-cycle error equals or is substantially equal to zero. The duty-cycle error equals or substantially equals zero when the duty cycles of the local clock signals equal or are substantially equal to fifty percent.