Delay-Locked Loop Control for Duty-Cycle-Independent Delay
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Solution Overview
Problem
Existing Delay-Locked Loops (DLLs) fail to maintain a constant delay time despite variations in the duty cycle of the clock signal, leading to instability in clock signal replication.
Innovation Solution
A DLL design that adjusts the capacitor charging and discharging rates proportionally with the duty cycle of the clock signal, ensuring the delay time remains constant through a control loop that balances charge and discharge amounts during each signal period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the DLL uses a fixed charging and discharging current ratio to set delay time, then the delay is programmable and stable under fixed duty cycle conditions, but the delay time varies when the duty cycle of the clock signal changes
Solution Approach 1:
The patent makes the charging current dynamic by modulating it according to the duty cycle of the clock signal. The charging current source is controlled to vary its output current in proportion to the duty cycle, while the discharging current remains fixed. This dynamic adjustment ensures that the delay time remains constant despite duty cycle variations, as the charging and discharging time periods scale proportionally with duty cycle changes
Solution Approach 2:
The patent changes the charging current parameter dynamically based on the duty cycle of the clock signal. By adjusting the charging current magnitude in proportion to duty cycle variations, the system maintains a constant delay time. The discharging current parameter remains unchanged, creating an asymmetric parameter adjustment strategy that resolves the duty cycle sensitivity issue
2Device complexity
If the DLL adjusts delay through capacitor charging/discharging with fixed currents, then the circuit is simple to implement, but the delay time is sensitive to duty cycle variations
Solution Approach 1:
The patent introduces dynamic control of the charging current while maintaining a fixed discharging current. This dynamic adjustment mechanism adds minimal circuit complexity (primarily a current control module) but significantly improves delay stability by compensating for duty cycle variations. The complexity increase is localized and targeted, rather than requiring complete circuit redesign
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The DLL maintains a substantially constant delay time across varying duty cycles, enhancing stability and reliability in clock signal replication, particularly in applications like multi-stage drivers for serial bus conductors.
Implementation Method 1
a capacitor that is charged at a first rate starting at a time of a first edge of the first signal and continuing until a time of an edge of the second signal
Data Source
Figure 1~3
Figure 2
Figure 4~5
AI summary
A Delay-Locked Loop (DLL) uses a delay line to delay a first signal by a "delay time", thereby generating a second signal. A capacitor is charged at a first rate starting at a first edge of first signal and continuing until an edge of the second signal. The capacitor is then discharged at a second rate until another edge of the first signal. A control loop controls the delay time such that the amount the capacitor is charged is the same as the amount the capacitor is discharged. The delay time is constant and is substantially independent of variations in the duty cycle of the first signal. In one example, duty cycle distortion cancellation is accomplished by changing the first rate proportionally with respect to changes in first signal duty cycle. In another example, the first and second rates are independent of the duty cycle of the first signal.