Delay-Locked Loop with Duty-Cycle-Independent Delay Control
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Solution Overview
Problem
Existing Delay-Locked Loops (DLLs) fail to maintain a constant delay time despite variations in the duty cycle of the clock signal, leading to instability in clock signal replication.
Innovation Solution
A DLL design that includes a capacitor charged and discharged at controlled rates, with a feedback loop ensuring the charge and discharge amounts are equal during each signal period, allowing the delay time to be set and maintained constant regardless of duty cycle changes through programming the ratio of charge and discharge rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a traditional DLL uses fixed charge and discharge currents for the capacitor, then the delay time can be programmed by setting the current ratio, but the delay time varies when the duty cycle of the clock signal changes
Solution Approach 1:
The patent makes the charge current dynamic by controlling it with the clock signal itself. The charge pump circuit responds to rising edges of the clock signal to charge the capacitor, and the charge amount automatically adapts to duty cycle variations. This dynamic adjustment ensures that the delay time remains stable regardless of duty cycle changes, while still allowing programmable delay through the current ratio setting.
Solution Approach 2:
The patent implements a feedback mechanism where the clock signal directly controls the charging process. The rising edges of the clock signal trigger charge pump operation, creating a self-regulating system that automatically compensates for duty cycle variations. This feedback loop ensures that the capacitor charges and discharges in a balanced manner, maintaining constant delay time despite input signal variations.
2Manufacturing precision
If the charge rate is increased to achieve a desired delay time, then the delay can be adjusted, but the delay becomes sensitive to duty cycle variations
Solution Approach 1:
The patent changes the operational parameters of the charge pump by controlling it with the clock signal edges rather than a fixed rate. This parameter change allows the system to adapt to different duty cycles while maintaining accurate delay timing. The charge amount becomes a function of the clock signal characteristics rather than a fixed parameter, enabling both precision and adaptability.
Data Source
AI summary
A Delay-Locked Loop (DLL) uses a delay line to delay a first signal by a “delay time”, thereby generating a second signal. A capacitor is charged at a first rate starting at a first edge of first signal and continuing until an edge of the second signal. The capacitor is then discharged at a second rate until another edge of the first signal. A control loop controls the delay time such that the amount the capacitor is charged is the same as the amount the capacitor is discharged. The delay time is constant and is substantially independent of variations in the duty cycle of the first signal. In one example, duty cycle distortion cancellation is accomplished by changing the first rate proportionally with respect to changes in first signal duty cycle. In another example, the first and second rates are independent of the duty cycle of the first signal.