Duty Cycle Error Calculation Circuit for Low-Jitter DLL Clocks
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Solution Overview
Problem
Conventional clock generators for synchronous integrated circuits face issues with clock jitter, high power consumption, and cumbersome size due to the cascaded structure of variable delays, which complicates synchronization and duty cycle correction, especially at higher frequencies.
Innovation Solution
A duty cycle correction circuit that includes a measuring circuit and a duty cycle error calculation circuit, allowing for parallel operation with the delay locked loop to reduce clock jitter and power consumption, and improve synchronization efficiency by adjusting the phase relationship between complementary clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a cascaded structure of variable delays is used for duty cycle correction, then duty cycle accuracy is improved, but clock jitter increases and power consumption increases
Solution Approach 1:
The patent divides the duty cycle correction function into two independent segments: a measuring circuit that detects duty cycle errors and a correction circuit that generates corrected clock signals. This segmentation allows the correction circuit to operate in parallel with the delay locked loop without requiring cascaded variable delays, thereby reducing clock jitter while maintaining duty cycle accuracy.
Solution Approach 2:
The patent transitions from a sequential cascaded structure to a parallel structure by introducing a new dimension of operation. The correction circuit operates simultaneously with the delay locked loop in parallel, rather than sequentially in cascade. This dimensional change eliminates the accumulation of jitter from multiple variable delay stages while achieving the same duty cycle correction objective.
2Manufacturing precision
If a cascaded structure of variable delays is used for duty cycle correction, then duty cycle accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the correction functionality into dedicated measuring and correction modules that operate independently in parallel. This eliminates the need for cascaded variable delay circuits and their associated control logic, significantly reducing device complexity while maintaining accurate duty cycle correction capability.
Solution Approach 2:
The correction circuit is designed to perform multiple functions: it measures duty cycle errors, generates correction signals, and outputs corrected clock signals. This multi-functionality consolidates what would otherwise require separate cascaded circuits into a single integrated module, reducing overall device complexity.
3Manufacturing precision
If a cascaded structure of variable delays is used for duty cycle correction, then duty cycle accuracy is improved, but power consumption increases
Solution Approach 1:
By segmenting the correction function into parallel measuring and correction circuits, the patent eliminates the need for multiple active variable delay stages that would consume power sequentially. The parallel architecture reduces cumulative power consumption while achieving the same correction accuracy.
Solution Approach 2:
The transition from sequential cascaded operation to parallel operation represents a dimensional change in the system architecture. This parallel dimension allows both the delay locked loop and correction circuit to operate simultaneously with minimal interaction, reducing the total power consumption compared to cascaded variable delays that would require multiple active stages.
Data Source
AI summary
A system and method for generating a correction signal for correcting duty cycle error of a first clock signal relative to a second complementary clock signal. Changes to a time difference between high- and low-portions of the first clock signal are detected and the correction signal is generated in response to and accordance with the detected changes.