Delay-Locked Loop Duty-Cycle Error Detection for Memory Clocks
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Solution Overview
Problem
Semiconductor circuits face challenges in maintaining a constant duty ratio of internal clocks due to variations in process, voltage, and temperature, leading to phase delays and operation errors, especially when the duty cycle correcting circuit is shorted to ground or power supply voltage.
Innovation Solution
A delay locked loop circuit with a duty cycle correcting block and an error detecting unit that compares voltages of pumping output nodes to detect operation errors, ensuring a constant duty ratio and preventing errors in semiconductor memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a duty cycle correcting function is used to maintain constant duty ratio, then the duty ratio stability is improved, but operation errors occur when the correction circuit is shorted to ground or power supply voltage
Solution Approach 1:
The patent applies preliminary action by performing error detection before the duty cycle correcting circuit is activated. The test mode detects potential short circuit errors in the pumping circuitry before normal operation begins, preventing operation errors that would occur if the circuit were activated in a defective state. This is achieved through a test signal generation circuit that activates before the main duty cycle correction function.
Solution Approach 2:
The patent introduces an intermediary test mode that mediates between the potential defect (short circuit) and the duty cycle correction function. The test mode acts as an intermediate step that detects errors without affecting the normal duty cycle correction operation. The test signal generation circuit serves as an intermediary mechanism that can identify defects without disrupting the main function.
2Stability of the object's composition
If the duty cycle correcting block operates continuously, then the duty ratio correction is maintained, but it becomes difficult to detect operation errors
Solution Approach 1:
The patent applies periodic action by implementing a test mode that operates periodically or on-demand rather than continuously. The test signal generation circuit can be activated at specific times (such as during initialization or through a test control signal) to detect errors without interfering with the continuous duty cycle correction function. This periodic testing approach allows error detection while maintaining continuous correction operation.
3Manufacturing precision
If process, voltage, and temperature variations occur, then the duty ratio varies causing phase delay, but adding correction complexity increases circuit complexity
Solution Approach 1:
The patent applies self-service by implementing a self-diagnostic capability within the duty cycle correcting circuit. The test signal generation circuit uses the existing circuitry (pumping capacitors, switching transistors) to detect its own potential failures without requiring external test equipment. The circuit tests itself by generating test signals and monitoring the responses, reducing the need for additional complex external testing infrastructure.
Data Source
AI summary
A delay locked loop circuit includes: a delay locked loop block receiving an external clock and generating a delay locked internal clock; a duty cycle correcting block connected to the delay locked loop block and correcting the duty cycle of the internal clock; and an error detecting unit comparing the voltages of first and second pumping output nodes of the duty cycle correcting block to detect an operation error of the duty cycle correcting block.