Delay-Locked Loop Feedback Duty Cycle Correction for High-Frequency Clocks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing DLLs face challenges with increased power consumption and chip area due to the addition of duty cycle correctors, which can cause clock signal distortion and limit the maximum operating frequency, especially when the input clock signal's duty cycle deviates from 50%.
Innovation Solution
A DLL with a duty cycle corrector positioned in the feedback path, including a phase and duty cycle detector, a duty cycle corrector, a control code generator, and a delay circuit, forms a feedback loop to adjust and maintain the duty cycle of the input clock signal, reducing power consumption and chip area by eliminating the need for a replica delay circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a duty cycle corrector is added to the DLL, then the duty cycle of the output clock signal is corrected, but the power consumption and chip area increase
Solution Approach 1:
The patent combines the duty cycle correction function with the existing delay circuit in the DLL feedback path. The delay circuit performs both phase adjustment and duty cycle correction simultaneously, eliminating the need for a separate duty cycle corrector circuit. This merging approach corrects duty cycle deviations while reducing power consumption and chip area.
2Manufacturing precision
If a duty cycle corrector is added to the DLL, then the duty cycle of the output clock signal is corrected, but the chip area increases
Solution Approach 1:
The patent merges the duty cycle correction functionality into the existing delay circuit that is already part of the DLL feedback path. By making the delay circuit perform dual functions (phase adjustment and duty cycle correction), the chip area is minimized without requiring additional dedicated duty cycle correction circuitry.
Solution Approach 2:
The delay circuit is designed to serve multiple purposes: it provides phase adjustment for clock skew correction and simultaneously performs duty cycle correction. This multi-functional approach allows a single circuit element to address both timing and duty cycle issues, reducing overall chip area.
3Speed
If the input clock signal has a high frequency and deviated duty cycle, then the clock signal may disappear through delay circuits, but the maximum operating frequency is limited
Solution Approach 1:
The patent applies duty cycle correction at the beginning of the feedback path, before the signal passes through multiple delay stages. By pre-correcting the duty cycle of the input clock signal, the signal maintains its integrity throughout subsequent delay operations, preventing signal disappearance even at high frequencies.
Solution Approach 2:
The patent implements a feedback mechanism where the output clock signal is monitored and fed back to adjust the duty cycle correction. This closed-loop feedback ensures that duty cycle deviations are continuously corrected, maintaining signal integrity and enabling reliable operation at maximum frequencies without signal loss.
Data Source
AI summary
A delayed locked loop (DLL) adjusts a duty cycle of an input clock signal and outputs an output clock signal. The DLL includes a phase and duty cycle detector configured to detect a phase and duty cycle of the input clock signal, a duty cycle corrector configured to correct the duty cycle, a control code generator configured to detect coarse lock of the DLL and generate a binary control code corresponding to the detection result, and a delay circuit configured to delay an output signal of the duty cycle corrector by a predetermined time according to the binary control code, tune the duty cycle thereof, and mix the phase thereof, wherein the phase and duty cycle detector, the duty cycle corrector, the control code generator, and the delay circuit form a feedback loop.