DLL Duty Cycle Correction Under Voltage Bump Locking Errors
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Solution Overview
Problem
In semiconductor devices, duty cycle distortions caused by voltage bumps can lead to abnormal DLL operation and failure, resulting in a degraded performance and potential loss of the desired DLL clock signal, especially in high-performance memory systems.
Innovation Solution
A delay locked loop (DLL) with an integrated duty cycle corrector (DCC) and a DCC controller that disables the DCC when a phase difference between delayed clock signals exceeds a preset time, ensuring stable operation by controlling the DCC phase mixer and dummy DCC phase mixer through detection units and signal generation circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a duty cycle corrector (DCC) is continuously operated to correct duty cycle distortions, then the duty cycle accuracy is improved, but the risk of abnormal operation and locking failure increases under voltage bumps
Solution Approach 1:
The DCC operation mode is dynamically switched between enabled and disabled states based on real-time phase difference detection. The system transitions from a static continuous operation mode to a dynamic conditional operation mode, activating the DCC only when phase differences indicate duty cycle distortion and disabling it when phase differences are within acceptable ranges, thereby preventing abnormal operations under voltage bumps while maintaining duty cycle accuracy when needed
Solution Approach 2:
A feedback mechanism is implemented where the phase difference between first and second delayed clock signals is continuously detected and used to control the DCC operation state. The detection unit monitors phase differences and feeds this information back to the control logic, which adjusts the DCC enable/disable state accordingly, creating a closed-loop control system that adapts to changing operating conditions and prevents locking failures
2Manufacturing precision
If the DCC is enabled to correct asymmetric clock signals, then the DLL clock signal duty cycle is maintained at 50%, but the complexity of the control system increases
Solution Approach 1:
The duty cycle correction function is extracted as a separate, independently controllable module (the DCC) that can be selectively activated or deactivated. By separating the DCC operation control from the main DLL operation and implementing it as an independent enabled/disabled function, the system adds minimal complexity only when correction is needed, while keeping the base system simple when the DCC is not required
Solution Approach 2:
The system performs preliminary detection of phase differences between clock signals before initiating DCC operation. By detecting phase differences in advance and determining whether correction is needed before actually enabling the DCC, the system avoids unnecessary complexity and activation, only engaging the correction mechanism when pre-detected conditions warrant its use
3Productivity
If the DLL operates at higher speeds to improve performance, then the data transfer rate is increased, but clock skew and duty cycle distortion increase
Solution Approach 1:
At higher operating speeds, the feedback mechanism becomes even more critical as phase differences and duty cycle distortions increase. The continuous monitoring of phase differences between first and second delayed clock signals and the dynamic adjustment of DCC operation state provides real-time correction that compensates for speed-related distortions, enabling high-speed operation while maintaining clock signal symmetry
Solution Approach 2:
The system dynamically changes the operational parameters of the DCC based on detected phase differences. When phase differences indicate duty cycle distortion (which increases at higher speeds), the DCC is enabled with specific delay adjustments; when phase differences are within acceptable ranges, the DCC is disabled. This parameter-based dynamic control allows the system to adapt to speed-related distortions
Data Source
AI summary
A delay locked loop (DLL) of a semiconductor device includes: a first delay line for delaying a first clock signal in synchronization with a first edge of an external clock signal to output a first delayed clock signal; a second delay line for delaying a second clock signal in synchronization with a second edge of the external clock to output a second delayed clock signal; a duty cycle corrector (DCC) for mixing phases of the first and second delayed clock signals to output a DLL clock signal with a corrected duty cycle; and a DCC controller for disabling the duty cycle corrector in a section during which a phase difference between the first and second delayed clock signals is greater than a preset time after a delay locking.