Delay Locked Loop Duty Cycle Compensation Reset
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Solution Overview
Problem
In high-speed synchronous semiconductor memory devices, such as DDR SDRAM, the delay locked loop (DLL) faces challenges in maintaining stable data transfer due to clock skew and distorted duty ratios, leading to faulty DLL clocks and abnormal device operation, especially when external and internal clocks are distorted or asymmetric.
Innovation Solution
A delay locked loop with a reset control block that compensates for phase differences between delay blocks, allowing for duty cycle compensation and resetting the loop if a predetermined phase difference exceeds a certain threshold after achieving a delay locking state, ensuring stable operation by adjusting the duty ratio of internal clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the delay locked loop operates with distorted external or internal clocks, then the DLL can generate faulty DLL clocks leading to abnormal device operation, but adding complex distortion detection and correction mechanisms increases device complexity
Solution Approach 1:
The patent applies preliminary action by detecting phase differences between first and second DLL clocks before they cause faulty operation. The reset control block continuously monitors the phase relationship and resets the DLL to an initial state when distortion is detected, preventing abnormal device operation before it occurs.
Solution Approach 2:
The patent implements feedback through a reset control block that continuously monitors the phase difference between DLL clocks and provides reset signals when distortion exceeds thresholds. This closed-loop feedback mechanism maintains reliability by automatically correcting distorted clock signals without requiring complex distortion detection circuits.
2Reliability
If the duty ratio of internal clock is distorted due to asymmetric input clock or internal operations, then data transfer stability deteriorates, but implementing duty cycle compensation increases device complexity
Solution Approach 1:
The duty cycle compensation block performs preliminary correction of distorted duty ratios by adjusting the widths of clock signals before they are used for data transfer. This ensures that even when input clocks are asymmetric or distorted, the internal DLL clocks maintain proper 50% duty cycles, guaranteeing stable data transfer without complex additional compensation circuits.
3Reliability
If the phase difference between first and second DLL clocks exceeds a predetermined amount after delay locking, then the DLL operation becomes unstable, but continuously monitoring and resetting increases power consumption
Solution Approach 1:
The reset control block implements periodic monitoring of phase differences between DLL clocks and resets the system only when necessary. This periodic check approach maintains stability by detecting and correcting phase excursions while minimizing power consumption by avoiding continuous active correction circuits.
4Loss of time
If a register controlled DLL is used to reduce initial delay locking time, then the delay locking speed improves, but the ability to handle distorted clocks and maintain duty ratio symmetry deteriorates
Solution Approach 1:
The patent segments the DLL into functionally independent blocks: a register controlled delay locking section for fast initial acquisition, and a separate duty cycle compensation section with reset control for maintaining reliability under distorted conditions. This segmentation allows the system to achieve fast locking while simultaneously maintaining robust distortion handling capabilities through specialized sub-circuits.
Data Source
AI summary
A delayed locked loop, capable of a duty cycle compensation, resets if a phase difference between outputs from delay blocks in the delay locked loop is over a predetermined amount after a delay locking state is achieved. The delay locked loop includes a duty cycle compensator for receiving first and second clocks and a reset control block for resetting the delay locked loop if a phase difference between the first and second clocks is over a predetermined amount after the delay locked loop achieves a delay locking state.