DLL Duty-Cycle Correction Using Integrated Delay Control
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Solution Overview
Problem
Existing DLL circuits face challenges in efficiently adjusting the duty of output clocks due to fabrication process variations, requiring redundant circuit configurations and lengthy processes to achieve optimal duty alignment, which increases circuit size and complexity.
Innovation Solution
A DLL circuit with a duty detection circuit and a duty change circuit that detects the duty ratio of output signals from variable delay circuits and adjusts the delay values based on the detection results, eliminating the need for redundant paths and simplifying the circuit configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a duty detection and correction circuit is provided on a succeeding stage of a variable delay circuit to adjust the duty of output clock, then the duty of the output clock can be brought into coincidence with the duty of the reference clock, but it takes much time for the duty adjustment process and the circuit size increases
Solution Approach 1:
The patent combines the duty detection and correction functions into a single integrated circuit that operates in parallel with the phase detection and correction circuit. This merging approach allows both duty and phase alignment to be achieved simultaneously without requiring separate sequential circuits, thereby reducing overall circuit size while maintaining accurate duty alignment.
Solution Approach 2:
The duty detection and correction operations are performed in parallel with phase detection and correction, rather than sequentially. This preliminary action approach allows the duty to be corrected before or during the phase locking process, eliminating the lengthy sequential adjustment process described in the background.
2Manufacturing precision
If a duty detection and correction circuit is provided on a succeeding stage of a variable delay circuit to adjust the duty of output clock, then the duty of the output clock can be brought into coincidence with the duty of the reference clock, but the sensitivity of the duty detection and correction circuit is insufficient
Solution Approach 1:
The patent introduces a duty correction signal as an intermediary that is generated based on the difference between the detected duty and the target duty. This intermediary signal is then used to control the duty correction circuit, which adjusts the pulse width of the output clock. This intermediary mechanism enhances the sensitivity and precision of duty detection and correction.
Solution Approach 2:
The duty detection circuit continuously monitors the duty of the output clock and feeds back the detected value to the duty correction circuit. This feedback mechanism allows for real-time adjustment of the duty, improving detection sensitivity and ensuring accurate duty alignment even in the presence of fabrication variations.
3Manufacturing precision
If phase lock is via two routes of the variable delay circuit and the duty detection and correction circuit, then the duty can be adjusted, but it becomes necessary to provide supplementary circuits such as PFD and CP2 in addition to PD and CP1
Solution Approach 1:
The patent merges the duty detection and correction functions into a single integrated circuit that operates in parallel with the phase detection and correction circuit. This merging approach allows both duty and phase alignment to be achieved simultaneously without requiring separate sequential circuits, thereby reducing overall circuit size while maintaining accurate duty alignment.
Solution Approach 2:
The duty correction circuit is designed to work in conjunction with the existing phase detection and correction circuit, allowing a single integrated system to perform both duty and phase alignment functions. This multi-functional approach eliminates the need for separate supplementary circuits while maintaining precise control over both duty and phase.
Data Source
AI summary
A DLL includes a first variable delay circuit that variably delays a first transition of an external signal, a second variable delay circuit that variably delays a second transition of the external signal, a synthesis circuit that synthesizes output signals of the first variable delay circuit and the second variable delay circuit, a duty change detection circuit that changes and detects the duty of an output signal of the synthesis circuit, and delay control circuits that vary the delay of the first variable delay circuit or the second variable delay circuit in accordance with the result of duty detection by the duty change detection circuit.