DLL Duty Ratio Correction for Low-Frequency PVT Variations
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Solution Overview
Problem
Existing DLL circuits in semiconductor memory apparatuses face challenges in accurately generating a clock with a predetermined duty ratio due to variations in Process, Voltage, and Temperature (PVT), leading to high power consumption and limited integration density, especially when handling low-frequency clock signals.
Innovation Solution
A DLL circuit with a duty ratio detection unit, correction control unit, and duty ratio correction unit that detects and corrects the duty ratio of both rising and falling clocks, and a phase mixing unit that selectively adjusts the clock phases to ensure accurate duty ratio generation, even under PVT changes and low-frequency conditions, without increasing component area or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a dual loop DLL circuit with phase mixer is used to control duty ratio, then duty ratio correction capability is improved, but circuit area and power consumption increase
Solution Approach 1:
The patent extracts the duty ratio correction function from the traditional phase mixer and implements it separately using a duty ratio correction unit that operates on the reference clock before it enters the delay lines. This separation allows duty ratio correction to be performed independently of phase adjustment, reducing the complexity and area of the overall circuit while maintaining correction capability.
Solution Approach 2:
The DLL circuit is segmented into distinct functional blocks: a duty ratio correction unit that corrects the reference clock duty ratio, delay lines for phase adjustment, and a phase mixer for fine phase control. This segmentation allows each block to be optimized independently, reducing overall circuit area while maintaining duty ratio accuracy.
2Manufacturing precision
If phase mixer with multiple drivers is used to correct duty ratio, then duty ratio control capability is improved, but power consumption increases
Solution Approach 1:
The duty ratio correction function is extracted from the power-consuming phase mixer drivers and implemented in a dedicated duty ratio correction unit. This unit uses simpler logic circuits rather than multiple high-power drivers, significantly reducing power consumption while maintaining duty ratio control accuracy.
Solution Approach 2:
The patent uses lightweight logic circuits and control signals instead of heavy-duty drivers for duty ratio correction. The correction is achieved through selective gating and logical operations rather than through multiple high-power transistor drivers, reducing power consumption.
3Manufacturing precision
If duty ratio correction is performed for low-frequency clock signals, then duty ratio accuracy is improved, but circuit area and power consumption increase
Solution Approach 1:
The duty ratio correction unit operates dynamically based on the frequency of the input clock signal. Correction is applied adaptively, with the circuit automatically adjusting its operation based on whether the input clock is low-frequency or high-frequency, allowing accurate correction without requiring additional circuitry for different frequency ranges.
Solution Approach 2:
The duty ratio correction unit is designed to handle both low-frequency and high-frequency clock signals using the same circuit architecture. This universal design corrects duty ratio for all input frequencies without requiring separate correction circuits, thereby avoiding increased circuit area.
Data Source
AI summary
A DLL circuit includes a duty ratio detection unit that detects a duty ratio of a rising clock and a duty ratio of a falling clock, thereby outputting a duty ratio detection signal. A correction control unit generates a correction control signal in response to the duty ratio detection signal. A duty ratio correction unit corrects a duty ratio of an internal. clock in response to the correction control signal, thereby outputting a reference clock.