DLL Clock Recovery Circuit for Low-Power Edge-Based Sampling
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Solution Overview
Problem
Existing clock recovery circuits for data transmission without a clock signal require complex and power-hungry analog-digital solutions, which are not suitable for low-power applications like automated toll payment systems.
Innovation Solution
A fully-digital clock recovery circuit using a Delay Locked Loop (DLL) and phase alignment features, activated only when valid data is received, with a rough data detector to check frequency ranges and generate a clock based on incoming data edges, reducing power consumption and eliminating the need for calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If precise local oscillators (PLL arrangements) are used for clock recovery, then good noise rejection and accurate sampling are achieved, but circuit complexity increases and power consumption rises
Solution Approach 1:
The patent replaces traditional analog PLL mechanisms with a fully digital delay-locked loop (DLL) approach. Instead of using analog oscillators and phase detectors, the invention uses digital delay elements and logic circuits to achieve clock recovery, thereby reducing circuit complexity while maintaining noise rejection capabilities
Solution Approach 2:
The invention changes the operating parameters by using a rough data detector to check frequency ranges before activating the DLL, and by implementing phase alignment features that adjust sampling points dynamically. This allows the system to achieve accurate clock recovery with simpler digital circuits rather than complex analog oscillators
2Measurement precision
If precise local oscillators (PLL arrangements) are used for clock recovery, then accurate data sampling is achieved, but power consumption increases
Solution Approach 1:
The patent implements periodic activation of the clock recovery function. The rough data detector periodically checks incoming data to determine if frequency is within expected range, and the DLL is activated only when valid data is detected. This periodic operation rather than continuous operation significantly reduces power consumption while maintaining sampling accuracy when needed
Solution Approach 2:
The system uses the incoming data itself to generate the clock signal through the DLL, rather than requiring an external power-hungry oscillator. The delay line is tuned using edges from the incoming data, and the reconstructed clock is derived directly from the data signal, making the system self-sufficient and low-power
3Productivity
If clock recovery is continuously active, then data can be recovered at any time, but power absorption increases
Solution Approach 1:
The patent implements conditional and periodic activation of clock recovery. The rough data detector continuously monitors incoming signals but only triggers the DLL activation when data is actually present and frequency is within expected range. This allows the system to be ready for data recovery without continuously powering the clock generation circuitry
Solution Approach 2:
The invention extracts and processes only the necessary components from the incoming signal. The rough data detector extracts frequency information to determine activation conditions, and the DLL is activated only when needed. This selective activation based on extracted signal characteristics reduces power absorption while maintaining productivity
Data Source
AI summary
A clock recovery circuit comprises an input node receiving a data signal having a data rate, and a digital oscillator producing a local clock signal with a frequency higher than the data rate. A counter clocked by the local clock signal has its count value sampled and reset at the rising and falling edges of the data signal, and a storage block coupled to the counter stores a count value that is updated in response to the current sampled count value of the counter lying in an update range between lower and upper bounds. A threshold value set is produced as a function of the updated count value stored in the storage block. Sampling circuitry receives and samples the data signal, and provides a sampled version of the data signal in response to the count value of the counter reaching any of the threshold values.