Delay-Locked Loop Edge Injection for False-Lock Prevention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Delay Locked Loops (DLLs) face challenges in locking the delay line to a stable time period, particularly when starting at a delay longer than the reference time period, leading to false locking or failure to lock, and require support circuitry to operate at high data rates, consuming more power and experiencing pulse evaporation issues.
Innovation Solution
A method and apparatus for locking a DLL that allows the delay line to lock from any starting delay state, including the longest delay state, by injecting only a single edge of a reference clock into the delay line, synchronizing it, and iteratively adjusting the delay until lock is achieved, using an injector, phase detector, and synchronizer to avoid initial minimum delay settings and pulse evaporation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the delay line starts at minimum delay setting, then the DLL can achieve lock, but the support circuitry must operate at much higher data rates causing increased power consumption
Solution Approach 1:
The delay line is pre-configured to start at maximum delay setting before the locking process begins. This preliminary action allows the support circuitry to operate at lower data rates during initialization, reducing power consumption while ensuring reliable lock acquisition.
Solution Approach 2:
The invention changes the operating parameter of the delay line from minimum delay to maximum delay at the start of the locking process. This parameter change allows support circuits to operate at reduced data rates, directly reducing power consumption while maintaining locking capability.
2Reliability
If the delay line starts at minimum delay setting, then the DLL can achieve lock, but pulse evaporation occurs when the input toggles faster than the delay line can handle
Solution Approach 1:
The delay line is pre-configured to maximum delay setting before locking, which is sufficiently long to prevent pulse evaporation. This preliminary configuration ensures that pulses can propagate through the delay line without being lost, while still allowing the DLL to achieve lock through the normal locking process.
Solution Approach 2:
By setting the delay line to maximum delay before operation, the invention applies a preliminary anti-action that prevents pulse evaporation from occurring in the first place. The maximum delay setting ensures that the delay line can handle the input toggling rate without losing pulses.
3Reliability
If the delay line starts at any delay state including maximum, then the DLL can lock without false locking, but the locking process must iteratively adjust the delay
Solution Approach 1:
The DLL uses a feedback mechanism where the phase detector continuously monitors the phase difference between the delay line output and reference clock, and the charge pump adjusts the delay line setting based on this feedback. This allows iterative adjustment from maximum delay to achieve accurate lock without false locking.
Solution Approach 2:
The delay line setting is made dynamic, allowing it to iteratively adjust from the maximum delay setting until lock is achieved. This dynamic adjustment process ensures accurate locking without false locking while adapting to the actual system conditions.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A method and apparatus for synchronizing a delay line to a reference clock includes a delay line that receives a clock input signal based on a reference clock and outputs a delay edge signal according to a control adjustment. An injector receives a first rise edge of the reference clock and in response to a first trigger, sends the clock input signal to the delay line. A synchronizer determines that the rise edge has passed through the delay line, and in response, sends the injector a second trigger to send a next single fall edge of the clock input signal to the delay line. A charge pump determines a timing difference between the delay edge signal and a reference edge signal sent from the injector. The charge pump sends the control signal to the delay line to adjust the delay setting of the delay line based on the timing difference.