Delay-Locked Loop Circuit With Extended Phase Lock Range
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Solution Overview
Problem
Conventional delay-locked loops (DLLs) have a limited lock range of −180 to +180 degrees, which restricts their operational reliability and flexibility in digital and mixed-signal systems.
Innovation Solution
The implementation of a delay-locked loop with an extended phase range, allowing the lock range to exceed 180 degrees, achieved by using a gater, phase-frequency detector, retimer, and loop filter to correctly determine the phase difference and adjust the delay line speed accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional delay-locked loop is used, then the circuit structure is simple, but the lock range is limited to −180 to +180 degrees
Solution Approach 1:
The phase detector is divided into multiple segments: a first phase-frequency detector for detecting frequency and phase differences, and a second phase detector for detecting phase differences. This segmentation allows each detector to handle specific portions of the phase range, thereby extending the overall lock range beyond the conventional −180 to +180 degrees while maintaining manageable circuit complexity through modular design
Solution Approach 2:
A retimer circuit is introduced as an intermediary component between the phase detectors and the delay line. The retimer receives timing signals from the phase detectors, processes them, and generates corrected timing signals that enable the system to handle phase differences outside the conventional range. This intermediary component facilitates the extended lock range without requiring complete redesign of the entire DLL structure
2Reliability
If the lock range is extended beyond −180 to +180 degrees, then the operational reliability is improved, but the device complexity increases
Solution Approach 1:
The phase detection function is segmented into multiple specialized detectors, each optimized for specific phase difference ranges. This allows the system to reliably handle extended phase differences while keeping each individual detector circuit relatively simple, thus improving operational reliability without proportionally increasing overall complexity
Solution Approach 2:
The retimer circuit serves multiple functions: it processes timing signals from different phase detectors, generates corrected timing signals, and coordinates the operation of various DLL components. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby improving reliability through comprehensive signal handling while limiting the increase in device complexity
3Measurement precision
If a conventional phase detector is used, then the circuit is simple, but it cannot correctly determine phase differences outside the −180 to +180 degree range
Solution Approach 1:
The phase detection task is segmented into multiple specialized detectors: a phase-frequency detector for detecting frequency and phase differences within a certain range, and an additional phase detector for detecting phase differences in extended ranges. Each detector is optimized for its specific detection range, ensuring measurement precision across the entire extended lock range while maintaining relatively simple individual detector circuits
Solution Approach 2:
The retimer acts as an intermediary that receives timing signals from the phase detectors, processes them to correct for detection limitations, and generates accurate timing signals that reflect the true phase differences. This intermediary processing ensures measurement precision for phase differences outside the conventional range without requiring the phase detectors themselves to be overly complex
Data Source
AI summary
An integrated circuit (IC) features a delay-locked loop (DLL) with a DLL signal input. The DLL comprises a delay line with multiple delay stages, a gater with clock input, and a phase-frequency detector (PFD). The delay line's signal input is linked to the DLL signal input, while the gater's inputs are connected to phase outputs of the delay line. The gater's clock input is tied to the DLL signal input, and its outputs feed into the PFD inputs. The PFD generates outputs that are used by a loop filter to control the speed of the delay line.