DLL False-Lock Detection and Stuck-Lock Avoidance
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Solution Overview
Problem
Lidar systems are prone to timing errors such as false-lock and stuck-lock conditions in their delay-locked loops (DLLs), which can lead to corrupted range data and unsafe operational conditions, particularly in safety-critical applications like automotive and aerospace.
Innovation Solution
A DLL false-lock detection system and stuck-lock avoidance system are implemented, utilizing a phase detector, charge pump, and loop filter to generate up and down pulses for controlling the delay line, along with a test pulse generator and shift register circuitry to identify and correct lock states, and edge-sensitive input circuitry to manage phase errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a delay-locked loop (DLL) is used to achieve fractional-clock time measurements, then measurement precision is improved, but timing errors such as false-lock and stuck-lock conditions occur
Solution Approach 1:
The patent implements a feedback mechanism where the output of the N-and gate is fed back to reset the phase detector, creating a self-correcting system that prevents false-lock conditions by continuously monitoring and correcting the lock state based on the actual phase relationship between reference and delay clock signals
Solution Approach 2:
The patent introduces an intermediary logic circuit (N-and gate) between the phase detector and delay line control that mediates the control signal generation. This intermediary detects false-lock conditions and blocks erroneous control signals, preventing the DLL from maintaining incorrect lock states
2Measurement precision
If the DLL phase detector continuously controls the delay line to minimize phase error, then measurement precision is improved, but stuck-lock conditions occur where the DLL becomes unrecoverable
Solution Approach 1:
The patent applies preliminary action by detecting potential stuck-lock conditions before they become unrecoverable. The N-and gate logic proactively identifies when the phase detector output would drive the delay line to extreme positions, and resets the phase detector in advance to prevent the stuck-lock state from establishing
Solution Approach 2:
The patent implements preliminary anti-action by using the N-and gate to generate a reset signal that counteracts the phase detector's erroneous control output before it can drive the delay line to a stuck position. This preliminary corrective action prevents the harmful stuck-lock condition from occurring
3Reliability
If multiple active pulse detection circuits are used to improve reliability, then system complexity increases
Solution Approach 1:
The patent segments the pulse detection function across multiple parallel active pulse detection circuits, each handling a specific time window or range bin. This segmentation allows independent operation of each detector, improving overall reliability through redundancy while maintaining manageable complexity through modular architecture
Data Source
AI summary
Systems, methods, and circuits provide delay-locked loop (DLL) timing error mitigation. A DLL false-lock detection system can include DLL circuitry configured to receive a reference clock signal having a time period. The system can include shift register circuitry and latched comparison circuitry which can determine a time period of a locked condition of the DLL delay line with respect to the reference clock signal time period. The system can determine whether the system is correctly locked to the base time period or incorrectly locked to a multiple of the base time period. A further system can operate to cause a phase detector circuitry in a DLL to ignore the first edge of a reference clock signal presented to the phase detector circuitry and thereby avoid stuck-lock conditions.