DLL Lock-Assist Circuit for False Lock Prevention
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Solution Overview
Problem
Conventional Digital Locked Loops (DLLs) face slow and error-prone acquisition processes, often resulting in false locking conditions, which hinder the precise alignment of input and output frequencies.
Innovation Solution
The DLL circuit incorporates a delay line, a control circuit, and an edge combiner, along with a voltage generator, phase frequency detector, loop filter, and charge pump, to selectively adjust the delay line based on phase and frequency differences, employing a lock assist mode to prevent false locking by modifying the delay line's input clock and using a programmable delay line to achieve precise frequency alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional DLL acquisition process is used, then the circuit structure is simple, but the locking speed is slow and false locking occurs frequently
Solution Approach 1:
The patent introduces a preliminary action mechanism where the control circuit proactively monitors frequency relationships between input and output clocks and preemptively switches the delay line input clock source before false locking can occur. This preliminary detection and switching action prevents the acquisition process from entering erroneous states, thereby improving locking speed and reliability without fundamentally redesigning the entire DLL structure.
Solution Approach 2:
The patent introduces a control circuit as an intermediary component that mediates between the delay line and the output. This control circuit acts as a smart intermediary that dynamically selects the delay line input clock source based on frequency relationships, preventing false locking without requiring complex modifications to the core delay line structure. The intermediary handles the complexity of false lock prevention centrally rather than distributing it throughout the entire circuit.
2Measurement precision
If the delay line is continuously adjusted to achieve precise frequency alignment, then frequency alignment accuracy improves, but the acquisition time increases
Solution Approach 1:
The patent implements periodic action by switching between two distinct operational modes: a coarse acquisition mode that quickly establishes approximate frequency alignment, and a fine-tuning mode that achieves precise frequency alignment. The control circuit periodically evaluates frequency relationships and switches modes accordingly, enabling the system to achieve high precision without continuously operating in the slow fine-tuning mode. This periodic switching between acquisition strategies reduces overall acquisition time while maintaining frequency alignment accuracy.
Solution Approach 2:
The patent applies dynamics by making the delay line input clock source dynamic rather than fixed. The control circuit dynamically switches between different clock sources (input clock and inverted output clock) based on real-time frequency relationships. This dynamic adaptation allows the system to optimize acquisition speed under different conditions, achieving precise frequency alignment more quickly by adapting the acquisition strategy to the current operational state rather than following a single slow continuous adjustment process.
3Manufacturing precision
If a programmable delay line is used to improve locking accuracy, then frequency alignment improves, but the device complexity increases
Solution Approach 1:
The patent utilizes parameter changes by making the delay line programmable, allowing dynamic adjustment of delay parameters to achieve precise frequency alignment. The control circuit programs the delay line with specific delay values based on detected frequency relationships, enabling high locking accuracy. This parameter-based control approach achieves precise locking without requiring complex hardware modifications, as the programmability allows flexible adaptation through software/control logic rather than structural complexity.
Data Source
AI summary
A DLL circuit is disclosed. The DLL circuit includes a delay line, configured to receive a delay line input clock, and to generate a plurality of output clocks each having a phase based on a delay of the delay line. The DLL circuit also includes a control circuit, configured to selectively cause the delay line input clock to be equal to one of a DLL input clock and an inverted one of the output clocks of the delay line, and an edge combiner, configured to generate a DLL output clock based on the output clocks of the delay line.