Delay-Locked Loop False-Lock Detection for Fast True Lock
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Solution Overview
Problem
Conventional delay-locked loops (DLLs) face issues with false-lock conditions, where they fail to achieve the desired 2π radians delay between internal and external clock signals, and require external reset signals for recovery, increasing complexity and synchronization time.
Innovation Solution
A DLL with a false-lock detection and recovery circuit that uses a phase detector, counter, delay circuit, and controller to modify the count value and select signal, allowing the DLL to detect and recover from false-lock conditions without an external reset, using only one intermediate clock signal to achieve true lock in a single iteration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a false-lock detection circuit is used to detect false-lock conditions, then the DLL can detect false-lock, but the complexity of the DLL increases and synchronization time increases
Solution Approach 1:
The false-lock detection functionality is extracted from the main DLL operation by using a separate read port to access the delay element states without interfering with the normal write operation. This allows independent detection of false-lock conditions while maintaining the simplicity of the main DLL structure.
Solution Approach 2:
A read port is introduced as an intermediary mechanism that allows the false-lock detection circuit to observe the state of delay elements without directly interacting with or complicating the main DLL control logic. This intermediary approach enables detection while preserving system simplicity.
2Reliability
If multiple intermediate clock signals are used to detect false-lock condition, then false-lock can be detected, but the time taken to achieve timing sign-off increases
Solution Approach 1:
Instead of using multiple intermediate clock signals for detection, the invention extracts the essential information by reading the state of delay elements directly through a read port. This extraction approach provides sufficient detection capability without the time overhead of generating and analyzing multiple clock signals.
Solution Approach 2:
The invention uses a partial approach by monitoring only the critical delay element states through the read port rather than analyzing all possible intermediate clock signals. This partial monitoring achieves adequate false-lock detection while significantly reducing the time required for timing sign-off.
3Measurement precision
If the DLL performs multiple iterations to achieve true lock, then accurate synchronization can be achieved, but the external clock signal synchronization time increases
Solution Approach 1:
The false-lock detection circuit performs preliminary detection of the delay element states before the DLL commits to a locked state. By detecting potential false-lock conditions in advance through the read port, the system can prevent unnecessary iterations and achieve true lock more quickly while maintaining synchronization accuracy.
Solution Approach 2:
The read port provides continuous feedback information about the state of delay elements to the false-lock detection circuit. This feedback mechanism allows the DLL to quickly identify false-lock conditions and adjust its operation to achieve true lock in fewer iterations, thereby reducing synchronization time while maintaining precision.
Data Source
AI summary
A DLL includes a phase detector, a counter, a delay circuit, and a false-lock detection and recovery circuit. The false-lock detection and recovery circuit checks whether the DLL is in a true-lock condition or not, based on an average of a phase difference between a clock signal and an intermediate clock signal. The intermediate clock signal is generated by the delay circuit based on a count value generated by the counter and a select signal generated by the false-lock detection and recovery circuit. The false-lock detection and recovery circuit generates and provides a control signal to the counter. Based on the control signal, the counter modifies the count on which a delay between the clock signal and an output signal of the DLL depends when the DLL is not in the true-lock condition.