Delay Locked Loop Feedback for Stable Clock Delay Alignment
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Solution Overview
Problem
Delay locked loop devices face issues with latency jumps due to unstable external voltage, affecting the delay time and requiring improved techniques for stable operation.
Innovation Solution
A delay locked loop device comprising a first delay line and a controller, where the controller adjusts the delay time based on multiple bits generated from a second delay line, frequency divider, and flip-flop circuits, using voltage levels to align rising edges and adjust the delay time effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the delay locked loop device uses external voltage for operations, then the device can function normally, but the delay time becomes unstable and latency jumps occur when the external voltage is not stable
Solution Approach 1:
The patent implements a feedback mechanism where the controller monitors the output signal from the delay line and compares it with the input clock signal. Based on this feedback, the controller dynamically adjusts the delay time to compensate for voltage-induced variations, thereby maintaining stable delay performance despite external voltage instability.
Solution Approach 2:
The patent changes the delay time parameter dynamically based on detected signal alignment. The controller modifies the delay time setting in response to voltage fluctuations, allowing the system to adapt to changing operating conditions and maintain reliable operation despite external voltage instability.
2Reliability
If the delay time is adjusted to compensate for voltage instability, then latency jumps are prevented, but the complexity of the control mechanism increases
Solution Approach 1:
The controller automatically detects misalignment between the output signal and input clock signal, and self-adjusts the delay time without external intervention. This self-service mechanism eliminates the need for complex external control circuits while maintaining delay stability.
Solution Approach 2:
The simple feedback loop compares the phase of the output signal with the input clock signal and automatically adjusts delay time accordingly. This minimal feedback mechanism achieves reliable delay stabilization without requiring complex control logic or additional hardware components.
Data Source
AI summary
A method includes following operations: a delay line delaying a first clock signal by a delay time to generate an output signal; a controller delaying the output signal by a first time interval to generate a first signal; the controller delaying the first clock signal by a second time interval shorter than the first time interval to generate a second clock signal; and the controller controlling the delay line according to the first signal and the second clock signal to adjust the delay time. A delay locked loop device is also disclosed herein.