Delay Locked Loop Feedback Divider for Low-Noise Clock Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional delay locked loops face issues with increased operating current, transient noise, and duty cycle distortion as clock speeds increase, affecting their accuracy and performance.
Innovation Solution
A delay locked loop system that includes a forward path with a variable delay line and a feedback loop with a frequency divider, allowing for reduced frequency operation of the feedback loop to minimize power consumption and noise, while maintaining synchronization of clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the feedback loop operates at high clock speeds to maintain synchronization accuracy, then the timing precision is improved, but the operating current and transient noise increase
Solution Approach 1:
The feedback loop operates periodically at a reduced frequency (e.g., divided by 2 or 4) rather than continuously at the full clock frequency. This periodic operation maintains synchronization accuracy over time while significantly reducing the average operating current and transient noise generated by the feedback path.
Solution Approach 2:
A frequency divider is introduced as an intermediary component between the delay locked loop output and the feedback path. This divider reduces the clock frequency fed back to the phase detector, thereby lowering power consumption and noise while still enabling effective phase comparison and delay adjustment.
2Measurement precision
If the feedback loop operates at high clock speeds, then the synchronization accuracy is improved, but the duty cycle distortion increases
Solution Approach 1:
By operating the feedback loop at a reduced periodic frequency, the system reduces the cumulative duty cycle distortion that would otherwise accumulate at higher frequencies. The lower operating frequency allows the duty cycle to stabilize between transitions, reducing distortion effects.
3Reliability
If the feedback loop is continuously enabled to maintain lock, then the synchronization is improved, but the transient noise increases
Solution Approach 1:
The feedback loop is enabled periodically at reduced frequency intervals rather than continuously at full frequency. This periodic enabling maintains the locked state and synchronization reliability while significantly reducing the transient noise that would be generated by continuous high-frequency operation.
Data Source
AI summary
Methods, devices, and systems are disclosed for a delay locked loop. A delay locked loop may comprise a delay line configured to receive a reference clock signal and output a delayed clock signal. The delay locked loop may also comprise a feedback loop including a frequency divider operably coupled to the delayed clock signal and configured to generate a frequency divided clock signal. Furthermore, the delay locked loop may include a phase detector configured to receive the reference clock signal and the frequency divided clock signal having a frequency less than that of the reference clock signal. Additionally, the phase detector may be configured to measure a phase difference of the reference clock signal and the frequency divided clock signal upon receipt of an active edge of the frequency divided clock signal.