Delay-Locked Loop Feedback Alignment for Precise DQS Timing
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Solution Overview
Problem
Existing delay locked loop circuits in memory standards face challenges in generating precise tDQSCK for aligning data strobe and clock signals, leading to inefficiencies and increased power consumption due to the direct use of replica drivers.
Innovation Solution
A delay locked loop circuit that includes a first and second delay line, a phase comparator, and control circuits to adjust delays, simulating the off-chip driver's delay without using a replica driver, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a replica driver is used to copy the off-chip driver on the feedback path, then the delay alignment accuracy is improved, but the power consumption increases
Solution Approach 1:
The patent creates a simplified copy of the off-chip driver's delay characteristics using a delay element in the feedback path, rather than copying the entire driver circuit. This delay element is configured to match the delay of the off-chip driver, achieving the necessary delay alignment accuracy while consuming significantly less power than a full replica driver would require.
2Use of energy by moving object
If the delay locked loop circuit uses a simplified delay simulation method, then the power consumption is reduced, but the delay alignment precision may be affected
Solution Approach 1:
The patent introduces a delay element as an intermediary component in the feedback path that specifically simulates the delay characteristic of the off-chip driver. This intermediary element bridges the gap between the simplified circuit architecture and the precise delay alignment requirement, enabling accurate delay matching without the need for complex replica driver circuits.
3Manufacturing precision
If the second delay line is adjusted to align with off-chip driver delay, then the tDQSCK signal precision is improved, but the device complexity increases
Solution Approach 1:
The patent segments the delay compensation function into two distinct parts: a first delay line for coarse delay adjustment and a second delay line for fine delay adjustment specifically targeting the off-chip driver delay. This segmentation allows each delay line to be optimized for its specific function, achieving high tDQSCK signal precision while keeping the overall circuit design manageable through clear functional division.
Data Source
AI summary
Provided are a delay locked loop circuit and an operating method, for providing an output clock signal to a bidirectional data strobe (DQS). The delay locked loop circuit includes: a first delay line, configured to delay an input clock signal to generate the output clock signal; a second delay line, configured to receive the output clock signal and delay the output clock signal to generate a feedback clock signal; a phase comparator, configured to compare phases of the input clock signal and the feedback clock signal to adjust a delay of the first delay line; and a control circuit, controlling the second delay line, configured to adjust a delay of the second delay line to be aligned to a delay of an off-chip driver (OCD) coupled to the DQS.