DLL Feedback Input Termination With Switched Load Impedance Matching
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Solution Overview
Problem
The existing reference output circuit faces challenges with electro-migration discrepancies between the output driver module and terminated load module, and the inability to update the terminated load module resistance during clock transitions, which introduces complexity and clock jitter.
Innovation Solution
The proposed solution involves a modified reference output circuit with a terminated load module that has increased resistance to match better with a passive resistor, allowing impedance matching and enabling updates during each clock cycle without disrupting the feedback clock signal, and using identical PMOS and NMOS transistors in the terminated load module to equalize electro-migration performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the terminated load module uses different PMOS and NMOS transistors to match output driver strength, then the driving capability is optimized, but electro-migration discrepancies occur between the output driver module and terminated load module
Solution Approach 1:
The patent applies different transistor sizing strategies to different circuits: the output driver module uses asymmetric PMOS and NMOS transistors for optimized driving capability, while the terminated load module uses symmetric PMOS and NMOS transistors with equal width to equalize electro-migration performance. This local differentiation resolves the contradiction by allowing each module to have optimal characteristics for its specific function.
2Measurement precision
If the terminated load module resistance is updated during clock transitions, then timing accuracy is improved, but complexity and clock jitter increase
Solution Approach 1:
The patent updates the terminated load module resistance in advance during the stable phase before clock transitions occur. By performing the resistance update preliminarily rather than during active clock edges, the circuit maintains timing accuracy while avoiding the complexity and jitter that would result from real-time updates during clock transitions.
3Adaptability or versatility
If the terminated load module resistance is updated during clock transitions, then impedance matching is improved, but clock jitter is introduced
Solution Approach 1:
The resistance update is performed in advance during the stable phase before clock transitions, ensuring impedance matching is achieved without disrupting the clock signal. This preliminary action maintains clock signal stability while still providing the adaptability of dynamic impedance matching.
Solution Approach 2:
The patent proactively updates the resistance before clock transitions occur, preventing potential impedance mismatches and their associated effects (such as signal reflections or timing errors) from occurring in the first place. This preliminary anti-action maintains both impedance matching and clock signal stability.
Data Source
AI summary
A reference output circuit for generating an output clock signal for driving signals off of an integrated circuit chip uses a switched terminated load in combination with an output buffer to generate a feedback clock signal, which is used, in combination with a reference input clock signal, to generate the output clock signal. The switched terminated load uses transistors having the same size as transistors in the output buffer. The switched terminated load draws the same DC current as the output buffer. As a result, the switched terminated load and the output buffer have the same electro-migration performance. Pull-up and pull-down MOS impedances of the switched terminated load are easily adjusted during switching periods of the switched terminated load. The design of the switched terminated load minimizes variations in the terminated load impedance due to MOS impedance variations.