Delay Locked Loop Feedback Switching for Faster Clock Synchronization
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in synchronizing internal clock signals with externally-generated clock signals due to time delays, requiring additional circuits that increase chip size and thermal dissipation, and existing methods either need duty cycle correction circuits or additional logic for successful synchronization.
Innovation Solution
A delay locked loop (DLL) circuit that selects a feedback quantity from a first intermediate location for initial synchronization and then switches to a second location for maintaining synchronization, reducing the need for additional circuits and logic, thereby achieving faster synchronization without increasing chip size or thermal dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If duty cycle correction circuits or additional logic are used for synchronization, then synchronization reliability is improved, but device complexity and chip size increase
Solution Approach 1:
The DLL circuit uses its own internal delay line to generate the feedback signal for phase detection, eliminating the need for external duty cycle correction circuits or additional logic. The delay line serves dual purposes: generating delayed clock signals and providing feedback for phase comparison, allowing the circuit to self-correct synchronization issues without external assistance
Solution Approach 2:
The delay line is designed to perform multiple functions: it generates delayed versions of the external clock signal for internal use and simultaneously provides a feedback signal for phase detection. This multi-functionality reduces the need for separate duty cycle correction circuits and additional logic, simplifying the overall device structure
2Measurement precision
If additional circuits are added for clock synchronization, then synchronization precision is improved, but thermal dissipation increases
Solution Approach 1:
The circuit uses internally-generated feedback signals from its own delay line rather than requiring additional external correction circuits, reducing the total number of active components and thereby reducing overall thermal dissipation while maintaining synchronization precision
Solution Approach 2:
The invention extracts the feedback signal directly from the delay line output and uses it for phase detection, eliminating the need for separate duty cycle correction circuits. This extraction approach reduces the number of circuits required, thereby reducing thermal dissipation
3Device complexity
If traditional DLL synchronization methods are used, then device simplicity is maintained, but synchronization speed is insufficient
Solution Approach 1:
The delay line is configured to provide a feedback signal that is already in the correct phase relationship with the external clock signal before phase detection occurs. This preliminary preparation of the feedback signal allows for faster phase comparison and synchronization lock, improving synchronization speed without adding complex circuits
Solution Approach 2:
The invention implements a feedback mechanism where the delay line output is fed back to the phase detector for continuous phase comparison with the external clock signal. This feedback loop enables rapid detection and correction of phase differences, significantly improving synchronization speed while maintaining device simplicity
Data Source
AI summary
Delay locked loop circuits and methods are disclosed. In the embodiments, a delay locked loop may include a phase detector to detect a phase difference between a clock signal and a reference clock signal, and a charge pump that receives the detected phase difference. A low pass filter may filter an output from the charge pump. The delay locked loop may further include a delay line having a plurality of delay elements, the plurality of delay elements including a first selectable group and a second selectable group that is larger than the first selectable group. A first clock signal from the first group of delay elements may be provided to the phase detector to first synchronize the delay locked loop, and following the synchronization, a second clock signal from the second group may be employed to synchronize the delay locked loop.