Delay-Locked Loop Filter Switching for Fast Lock and Low Jitter
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Solution Overview
Problem
Closed-loop clock circuits, such as phase-locked and delay-locked loops, face a trade-off between jitter and acquisition time, where reducing jitter increases acquisition time and vice versa, limiting the ability to optimize both simultaneously, especially in high-speed systems where phase error variations require dynamic adjustment of loop bandwidth.
Innovation Solution
A delay-locked loop with a variable loop bandwidth based on phase error, controlled by a filter whose depth and type are adjusted according to the phase error, allowing for reduced acquisition time when phase errors are large and reduced jitter when phase errors are small, thereby optimizing both parameters dynamically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If loop bandwidth is increased, then acquisition time is reduced, but jitter is increased
Solution Approach 1:
The patent implements dynamic loop bandwidth adjustment by switching between multiple filter depths based on phase error magnitude. The system transitions from a static filter configuration to a dynamic one where the filter depth (and thus loop bandwidth) changes in response to operating conditions. Specifically, when phase error exceeds a threshold, a shallower filter (higher bandwidth) is selected to accelerate acquisition; when phase error is within tolerance, a deeper filter (lower bandwidth) is selected to reduce jitter.
Solution Approach 2:
The patent changes the filter depth parameter of the loop filter based on phase error conditions. By adjusting this parameter, the system modifies the loop bandwidth dynamically. The filter depth serves as a controllable parameter that directly influences the trade-off between acquisition time and jitter, allowing the system to optimize performance according to real-time phase error measurements.
2Manufacturing precision
If loop bandwidth is decreased, then jitter is reduced, but acquisition time is increased
Solution Approach 1:
The system dynamically adjusts loop bandwidth by selecting different filter depths based on phase error magnitude. During the acquisition phase when phase error is large, the system uses a shallower filter to maintain faster response. Once locked and operating normally with small phase errors, the system switches to a deeper filter to minimize jitter, thus dynamically adapting to operational requirements.
Solution Approach 2:
The filter depth parameter is changed based on operational phase. During acquisition, a smaller filter depth (higher bandwidth) is used. During normal operation, a larger filter depth (lower bandwidth) is applied. This parameter change allows the system to optimize for either acquisition speed or jitter performance depending on the current state.
3Device complexity
If a single loop bandwidth is used, then circuit simplicity is maintained, but inability to optimize both jitter and acquisition time simultaneously
Solution Approach 1:
The patent segments the filtering function into multiple discrete filter depth options rather than using a single continuous adjustment mechanism. By providing a plurality of selectable filter depths (e.g., first depth, second depth), the system achieves adaptive performance while maintaining relative circuit simplicity through discrete selection rather than continuous control.
Solution Approach 2:
The loop filter is designed to serve multiple functions by incorporating multiple filter depths within a single circuit structure. This multi-functional filter can operate in different modes (acquisition mode with higher bandwidth, tracking mode with lower bandwidth) without requiring separate filter circuits, thus achieving adaptability while maintaining circuit simplicity.
Data Source
AI summary
Circuits, methods, and apparatus that vary one or more attributes or parameters of a closed-loop clock circuit as a function of a characteristic of its phase error. One example provides a delay-locked loop having a loop bandwidth that can be varied as a function of its phase error. In this specific example, current phase error is determined. This determination may be made directly, either by measuring phase error, or indirectly, by determining if phase error is within one or more ranges of values. Once the phase error is determined, the loop bandwidth can be set. In one example, the loop bandwidth is set by adjusting the depth, type, or depth and type of the delay-locked loop's loop filter. In this way, large phase errors can be reduced quickly by increasing loop bandwidth, while small phase errors can be used to decrease loop bandwidth, thereby improving jitter performance.