DLL Frequency Synthesizer for Fractional Clock Division
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional digital frequency synthesizers in integrated circuits are limited in resolution due to their reliance on voltage-controlled oscillators and integer division, failing to meet non-integer clock frequency requirements of functional circuits, and suffer from high complexity and power consumption.
Innovation Solution
A digital frequency synthesizer utilizing a combination of delay-locked loops (DLLs) and output delay chains to generate fractional-divided clock signals with adjustable duty cycles, allowing for precise frequency division and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If voltage-controlled oscillators and integer division are used in digital frequency synthesizers, then the device can generate clock signals, but the resolution is limited and cannot meet non-integer clock frequency requirements
Solution Approach 1:
The patent divides the frequency division function into two independent modules: an integer division module that performs integer division of the reference clock frequency, and a fractional division module that performs fractional division based on feedback. This segmentation allows the system to achieve both integer and fractional frequency division capabilities, resolving the contradiction between limited resolution and adaptability.
2Reliability
If conventional digital frequency synthesizers are used, then clock signals can be generated, but the complexity and power consumption are high
Solution Approach 1:
The patent merges the integer division module and fractional division module into a unified frequency synthesizer system with a shared reference clock input and coordinated operation. The integer division module divides the reference clock by an integer factor, while the fractional division module further divides the resulting signal by a fractional factor. This merging approach reduces overall system complexity compared to using separate independent oscillators for each division ratio.
3Reliability
If conventional digital frequency synthesizers are used, then clock signals can be generated, but power consumption is high
Solution Approach 1:
The patent implements dynamic control of the frequency synthesis process by allowing the integer and fractional division ratios to be independently adjusted based on the required output frequency. The system dynamically selects optimal division combinations to minimize power consumption while meeting frequency requirements, rather than using a fixed high-power oscillation approach.
4Device complexity
If integer division only is used, then the synthesizer structure is simple, but it cannot meet non-integer clock frequency requirements of functional circuits
Solution Approach 1:
The patent introduces a fractional division module as an intermediary stage between the integer division module and the output. The integer division module first reduces the reference clock frequency by an integer factor, and then the fractional division module applies additional fractional division to achieve the final non-integer frequency ratio. This intermediary approach enables precise frequency control while maintaining reasonable system complexity.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A digital frequency synthesizer includes a delay-locked loop (DLL) that generates time-delayed versions of a reference clock signal, a clock divider that executes an integer-division operation on one delayed clock signal to generate an integer-divided clock signal, and control circuitry that generates fractional data for enabling a fractional division. The digital frequency synthesizer further includes a first clock selector that selects one delayed clock signal as a DLL clock signal based on the fractional data, a delay chain that generates time-delayed versions of the DLL clock signal, and a second clock selector that selects one delayed clock signal as a selected clock signal based on the fractional data. A rising edge of the integer-divided clock signal is adjusted based on the selected clock signal to generate a fractional-divided clock signal that is a fractional-divided version of the reference clock signal.