DLL Frequency Locking for Fast Memory Power-Saving Switches
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Solution Overview
Problem
Delay locked loops (DLLs) in electronic devices, such as memory chips, face limitations in power savings due to their inability to reliably respond to rapid changes in clock frequency, restricting frequency slewing options and leading to slow and limited power reduction methods.
Innovation Solution
Implementing a method to lock the DLL at a slow clock frequency and instantaneously switch to an integer-multiplied frequency, allowing for faster frequency changes between normal operation and power saving modes without losing lock point, thereby achieving substantial power reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gradual frequency adjustments are used to maintain DLL locking, then reliability of DLL operation is improved, but speed of frequency switching deteriorates and device complexity increases
Solution Approach 1:
The DLL is initially locked at a low frequency before operation. This preliminary locking action establishes a stable reference state that enables subsequent rapid frequency multiplication without requiring gradual adjustments, thus achieving both reliability and speed
2Reliability
If gradual frequency adjustments are used to maintain DLL locking, then reliability of DLL operation is improved, but device complexity increases
Solution Approach 1:
The DLL is initially locked at a low frequency before operation. This preliminary locking action establishes a stable reference state that enables subsequent rapid frequency multiplication without requiring gradual adjustments, thus achieving both reliability and speed
Solution Approach 2:
The system changes the operating frequency parameter by multiplying the base frequency by an integer factor. This parameter change approach allows rapid frequency switching while maintaining DLL lock, avoiding the need for complex gradual adjustment mechanisms
3Use of energy by moving object
If rapid frequency changes are implemented, then power savings are improved, but DLL locking reliability deteriorates
Solution Approach 1:
The DLL is initially locked at a low frequency before operation. This preliminary locking action establishes a stable reference state that enables subsequent rapid frequency multiplication without requiring gradual adjustments, thus achieving both reliability and speed
Solution Approach 2:
The system changes the operating frequency parameter by multiplying the base frequency by an integer factor. This parameter change approach allows rapid frequency switching while maintaining DLL lock, avoiding the need for complex gradual adjustment mechanisms
Data Source
AI summary
A system and method are disclosed to accomplish power savings in an electronic device, such as a memory chip, by performing selective frequency locking and subsequent instantaneous frequency switching in the DLL (delay locked loop) used for clock synchronization in the electronic device. By locking the DLL at a slow clock frequency, the operational frequency may be substantially instantaneously switched to an integer-multiplied frequency of the initial locking frequency without losing the DLL lock point. This DLL locking methodology allows for faster frequency changes from higher (during normal operation) to lower (during a power saving mode) clock frequencies without resorting to gradual frequency slewing to conserve power and maintain DLL locking. Hence, a large power reduction may be accomplished substantially instantaneously without adding complexity to the system clock generator. Because of the rules governing abstracts, this abstract should not be used in construing the claims.