DLL Clock Frequency Switching for Faster Delay Locking
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Solution Overview
Problem
DLL circuits in semiconductor integrated circuits face challenges in reducing the time required for clock delay locking operations, which can lead to erroneous operations due to PVT variations, affecting synchronization and test efficiency.
Innovation Solution
An apparatus and method that includes a frequency multiplier to increase the external clock frequency, a period determinator to generate a signal indicating a predetermined period elapsed, and a frequency selector to control the clock input buffer with a power-up signal and period determination signal, allowing for faster delay locking by selectively transmitting either the high-frequency or external clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DLL circuit performs delay locking operation on the external clock, then the internal clock phase is advanced relative to the external clock, but the locking time becomes excessively long due to PVT variations
Solution Approach 1:
The patent applies preliminary action by pre-charging the capacitor connected to the phase detector before the delay locking operation begins. This initial charging state reduces the time required for the phase detector to accurately detect phase differences during the locking process, thereby reducing the overall delay locking time while maintaining synchronization accuracy under PVT variations.
Solution Approach 2:
The patent implements periodic action through the oscillating signal generated by the ring oscillator, which provides periodic feedback to the phase detector. This periodic signal enables continuous phase comparison and adjustment, allowing the DLL circuit to achieve and maintain accurate synchronization while reducing the time to complete the locking operation.
2Reliability
If the DLL circuit extends the delay locking operation time to ensure accurate locking under PVT, then synchronization accuracy is maintained, but test efficiency of the semiconductor integrated circuit deteriorates
Solution Approach 1:
By pre-charging the capacitor in the phase detector before the delay locking operation, the circuit achieves faster phase detection and locking convergence. This reduces the time the DLL circuit occupies during test modes, allowing other test areas to be executed concurrently or sequentially without prolonged waiting, thereby improving overall test efficiency while maintaining locking accuracy.
3Device complexity
If the DLL circuit uses a fixed delay locking mechanism, then the circuit structure remains simple, but the locking time cannot be reduced under varying PVT conditions
Solution Approach 1:
The patent introduces a capacitor connected to the phase detector that can be pre-charged before the delay locking operation. This additional element, while slightly increasing circuit complexity, enables faster phase detection and reduces locking time under PVT variations through a relatively simple mechanism.
Solution Approach 2:
The ring oscillator generates a periodic signal that feeds back to the phase detector, creating a continuous feedback mechanism. This periodic action enables dynamic adjustment during the locking process, allowing the circuit to adapt to PVT variations and reduce locking time without requiring complex control logic.
Data Source
AI summary
A frequency multiplier increases the frequency of an external clock and outputs a high-frequency external clock. A period determinator determines whether or not a predetermined period of the external clock elapses and outputs a period determination signal. A frequency selector selectively transmits the external clock or the high-frequency external clock to a clock input buffer under the control of a power-up signal and the period determination signal.