Delay-Locked Loop Frequency Switching for Low-Standby Power
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Solution Overview
Problem
Existing delay-locked loops consume high power due to continuous operation in both active and standby states, which is inefficient for maintaining data accuracy in DRAM systems.
Innovation Solution
A delay-locked loop design with a secondary path for frequency division and a primary path for outputting a clock replica signal, where the secondary path adjusts the frequency from a first frequency to a lower second frequency in standby mode, reducing power consumption without affecting output accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the delay-locked loop operates in a high-frequency state to ensure data accuracy, then the synchronization accuracy is improved, but the power consumption increases
Solution Approach 1:
The patent applies dynamics by making the operating frequency of the delay-locked loop adjustable rather than fixed. The loop dynamically switches between a first frequency (higher) and a second frequency (lower) based on operational state. This resolves the contradiction by allowing high frequency for accuracy when needed and low frequency for power savings when not needed, making the system adaptive to different operational requirements.
Solution Approach 2:
The patent changes the frequency parameter of the delay-locked loop based on operational state. By adjusting the frequency from a first frequency to a second frequency according to whether the system is in active or standby mode, the patent simultaneously optimizes both accuracy (when high frequency is used) and power consumption (when low frequency is used), resolving the technical contradiction between these two parameters.
2Reliability
If the delay-locked loop maintains high-frequency operation in standby state to ensure data accuracy, then the synchronization reliability is improved, but the standby current increases
Solution Approach 1:
The patent makes the standby state dynamic by switching the operating frequency based on whether the system is actively processing data or in standby. During standby, the loop operates at a lower second frequency that consumes less current while still maintaining sufficient synchronization reliability. When data processing is needed, it switches to the first frequency for high-speed operation, thus resolving the contradiction between reliability and energy loss in standby state.
Solution Approach 2:
The patent implements periodic switching between different operating frequencies based on data processing needs. The delay-locked loop alternates between high-frequency operation (first frequency) during active data processing and low-frequency operation (second frequency) during standby periods. This periodic action ensures reliability when needed while minimizing energy loss during standby, resolving the contradiction between these two parameters.
3Manufacturing precision
If the delay-locked loop operates continuously at high frequency to maintain synchronization, then the timing precision is improved, but the energy efficiency deteriorates
Solution Approach 1:
The patent applies dynamics by making the operating frequency adjustable based on operational requirements. The delay-locked loop dynamically switches between a first frequency for high timing precision during active operation and a second frequency for energy efficiency during standby. This dynamic adjustment resolves the contradiction by ensuring high timing precision is maintained only when actually needed, while improving energy efficiency during periods when full precision is not required.
Solution Approach 2:
The patent changes the frequency parameter based on operational state to balance timing precision and energy efficiency. By adjusting from a first frequency to a second frequency according to whether the system is active or in standby, the patent achieves high timing precision during data processing while improving energy efficiency during standby periods, thus resolving the contradiction between these two parameters.
Data Source
AI summary
The present disclosure relates to the technical field of integrated circuits, and specifically to a delay-locked loop, a control method for a delay-locked loop, and an electronic device. The delay-locked loop includes: a secondary path configured to perform frequency division on an input clock signal to generate a frequency-divided clock signal, adjust the frequency-divided clock signal having a first frequency to obtain an output clock signal in a locking process of the delay-locked loop, and adjust the frequency-divided clock signal to make the frequency-divided clock signal have a second frequency when the delay-locked loop is locked in a standby state, wherein the second frequency is lower than the first frequency; and a primary path configured to output, when obtaining a target instruction, an output clock replica signal having a same phase as the output clock signal.