Delay-Locked Loop Gating Scheme for Wider Phase Lock Range
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Solution Overview
Problem
Conventional delay-locked loops (DLLs) have a limited lock range of −180 to +180 degrees, which restricts their frequency range and operating conditions due to the phase detector's inability to distinguish between present and future clock pulses, leading to instability when phase differences exceed half a cycle.
Innovation Solution
The implementation of a delay-locked loop with an extended phase range, incorporating a gater, phase-frequency detector, retimer, and loop filter, which allows for a lock range larger than 180 degrees by correctly determining the order of phase signals even when the phase difference exceeds 180 degrees, using a gater to remove initial pulses and a phase-frequency detector to generate a speed control signal for the delay line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional phase detector is used in the DLL, then the circuit structure remains simple, but the lock range is limited to −180 to +180 degrees
Solution Approach 1:
The phase detection function is segmented into multiple components: a gater that segments the phase signals into separate pulse streams, and a phase-frequency detector that processes each segment independently. This segmentation allows the system to handle phase differences beyond the conventional ±180 degree range by treating different phase regions separately.
Solution Approach 2:
The gater acts as an intermediary component between the delay line and the phase-frequency detector. It mediates the phase signals by removing initial pulses and generating separate pulse streams that enable the PFD to correctly determine phase order even when phase difference exceeds 180 degrees, thus extending the lock range without requiring a complete redesign of the core PFD architecture.
2Adaptability or versatility
If the phase difference exceeds 180 degrees, then the frequency range can be extended, but the DLL becomes unstable due to inability to distinguish present and future clock pulses
Solution Approach 1:
The gater performs preliminary action by removing initial pulses from the phase signals before they reach the phase-frequency detector. This preliminary processing prevents the ambiguity that would otherwise cause instability, allowing the DLL to maintain stability even when operating with phase differences exceeding 180 degrees and thus extending the usable frequency range.
Solution Approach 2:
The phase-frequency detector provides feedback about the relative timing of phase signals, and this feedback is used by the loop filter to adjust the delay line speed. The system maintains stability by continuously monitoring phase relationships and making real-time adjustments, enabling reliable operation across an extended frequency range beyond conventional limits.
Data Source
AI summary
A DLL includes a delay line with two phase outputs, a gater coupled with the delay line phase outputs, a PFD coupled with gater outputs, a PD coupled with PFD outputs, a retimer coupled with PD outputs, and a loop filter with inputs coupled with the retimer and a speed control output coupled with the delay line. The gater passes signals on its two inputs to its two outputs, apart from a first pulse on its first input. The PD determines if the second gated signal leads or lags the first gated signal. The retimer retimes PD output signals to be aligned with a delay line input signal. The loop filter uses the retimed PD output signals to determine if the delay line should delay more or delay less, and outputs a speed control signal to control the delay line speed.