DLL Locking Circuit for Harmonic and False Lock Detection
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Solution Overview
Problem
Existing delay-locked loop (DLL) systems face challenges in maintaining stability and accurately detecting false locks and harmonic locks, which can lead to synchronization issues and data transmission errors.
Innovation Solution
The proposed solution involves a circuit and system design that includes a phase detector, a harmonic detector, and a false lock detector. These components work together to produce signals that indicate whether the DLL is properly locked, experiencing a false lock, or a harmonic lock, allowing for corrective actions to be taken.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional DLL locking detection is used, then the circuit complexity is low, but the reliability of lock detection is insufficient due to inability to distinguish false locks and harmonic locks
Solution Approach 1:
The lock detection function is segmented into three independent detectors: a phase detector for basic phase difference detection, a harmonic detector for detecting harmonic lock conditions by monitoring specific clock phases, and a false lock detector for identifying false lock states. Each detector operates independently with its own detection logic and output signals, allowing the system to reliably distinguish between different lock states without requiring a completely redesigned complex circuit.
Solution Approach 2:
The patent introduces intermediary detection mechanisms between the reference clock and feedback clock paths. The harmonic detector uses intermediary clock phases (first clock phase and second clock phase) to detect harmonic conditions, while the false lock detector uses additional clock phases (third and fourth clock phases) as intermediaries to identify false lock states. These intermediary detections provide additional information layers that improve reliability without directly complicating the core DLL structure.
2Measurement precision
If no harmonic detection is implemented, then the device complexity is low, but the accuracy of synchronization detection deteriorates due to undetected harmonic locks
Solution Approach 1:
The harmonic detector performs preliminary detection of harmonic lock conditions by continuously monitoring the relationships between the reference clock, feedback clock, and intermediate clock phases. By detecting harmonic conditions in advance through these preliminary phase comparisons, the system can identify harmonic locks before they cause synchronization errors, improving detection accuracy without requiring complex post-detection analysis.
Solution Approach 2:
The harmonic detector implements partial detection by focusing on specific critical clock phases (first and second clock phases) rather than analyzing all possible phase relationships. This selective monitoring of key phases provides sufficient accuracy for harmonic lock detection while keeping the detector complexity manageable, applying the principle of doing just enough detection where it matters most.
3Stability of the object's composition
If the DLL operates without false lock detection, then the ease of operation is high, but the stability of the system deteriorates due to undetected false locks causing data transmission errors
Solution Approach 1:
The false lock detector implements a feedback mechanism that continuously monitors the DLL operation and provides feedback signals when false lock conditions are detected. By comparing the third and fourth clock phases against expected relationships, the detector generates feedback that indicates false lock states, allowing the system to maintain stability by identifying and correcting false lock conditions without requiring complex manual intervention or system redesign.
Data Source
AI summary
A circuit includes a phase detector configured to produce a first up signal and a first down signal based on a difference between a reference clock and a feedback clock and a harmonic detector coupled to the phase detector, the harmonic detector configured to produce a second up signal based on the first up signal and whether the harmonic detector detects a harmonic lock between the reference clock and the feedback clock based on a first clock phase and a second clock phase. Additionally, the circuit includes a false lock detector coupled to the phase detector and to the harmonic detector, the false lock detector configured to produce a second down signal based on the first down signal and whether the false lock detector detects a false lock between the reference clock and the feedback clock based on a third clock phase and a fourth clock phase.