Delay Locked Loop Initial Delay Setting to Prevent Harmonic Locking
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Solution Overview
Problem
As semiconductor devices miniaturize, process variations lead to challenges in generating clock signals with accurate phase delay and constant duty cycle, increasing the likelihood of harmonic locking during high-speed data transmission.
Innovation Solution
A delay locked loop (DLL) comprising a delay line, edge combiner, fine tuning block, and mode control block, which includes ring oscillators, edge counters, and phase detectors, to generate a clock signal with a frequency twice that of the reference clock signal, ensuring accurate phase delay and constant duty cycle while preventing harmonic locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the frequency of the internal clock signal is increased to increase data transmission speed, then productivity is improved, but harmonic locking occurs during DLL locking operation and reliability deteriorates
Solution Approach 1:
The patent applies preliminary action by setting an initial delay value in the delay blocks before the locking operation begins. This initial delay is configured to be approximately 1/4 of the period of the reference clock signal, which pre-position s the phase of the output clock signal to prevent harmonic locking from occurring during the locking process. By preparing the delay configuration in advance, the system achieves high-frequency operation without falling into harmonic locking states.
2Area of moving object
If microminiaturization of manufacturing technology is implemented to decrease device size, then area is reduced, but process variation increases and manufacturing precision deteriorates
Solution Approach 1:
The patent employs parameter changes by dynamically adjusting the delay amount of each delay block based on detected phase differences. The delay blocks can modify their delay characteristics in response to control signals from the fine tuning block, allowing the system to compensate for phase delay mismatches caused by process variation. This dynamic parameter adjustment enables accurate phase control despite manufacturing variations in miniaturized devices.
Solution Approach 2:
The patent implements feedback through the fine tuning block, which continuously detects the phase difference between the reference clock signal and the output clock signal. Based on this feedback information, the system adjusts the delay amounts of individual delay blocks to minimize phase errors. This closed-loop feedback mechanism compensates for phase delay inaccuracies introduced by process variation in miniaturized manufacturing.
3Productivity
If the frequency multiplication is implemented to generate higher frequency clock signal, then productivity is improved, but phase delay accuracy and duty cycle constancy become more difficult to maintain
Solution Approach 1:
The patent applies segmentation by dividing the frequency multiplication process into multiple independent delay blocks, each contributing a specific phase delay. Instead of using a single large delay element, the system uses multiple smaller delay blocks (e.g., four blocks for 2x frequency multiplication), each delaying the signal by a quarter period. This segmentation allows independent control and fine-tuning of each block's delay characteristic, maintaining overall phase accuracy despite frequency multiplication.
Solution Approach 2:
The patent uses parameter changes by dynamically adjusting the delay amount of each segmented delay block based on the detected phase difference. The fine tuning block modifies the delay parameters of individual blocks to compensate for phase errors introduced during frequency multiplication. This dynamic parameter adjustment ensures that the output clock signal maintains accurate phase delay and constant duty cycle even at multiplied frequencies.
Data Source
AI summary
A delay locked loop controls a plurality of delay blocks included in a delay line and thus generate a plurality of clock signals which have a frequency obtained by multiplying a frequency of a reference clock signal, an accurate phase delay, and a constant duty cycle. The delay locked loop calculates an initial delay value and applies it to the delay blocks, thereby preventing harmonic locking and reducing locking time.