Delay-Locked Loop Hold Control for Stable Power-Down Phase

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Solution Overview

Problem

Conventional delay locked loops experience phase differences and lock failures during power down modes due to voltage fluctuations, leading to errors in data input/output characteristics.

Innovation Solution

A DLL hold control unit is introduced to receive a control signal and output a DLL hold control signal, fixing the delay time of the DLL variable delay unit, ensuring a consistent DLL clock signal phase across power down and other modes by applying a fixed delay time before power down.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the delay locked loop updates the phase of the DLL clock during power down mode, then the DLL clock phase can be corrected, but voltage fluctuations cause phase differences and lock failures

Engineering Contradiction:

ImproveDLL lock stabilityVSAvoidDLL clock phase consistency

Core Design Contradiction:

ReliabilityVSStability of the object's composition

Solution Approach 1:

The invention applies preliminary action by fixing the delay time of the DLL variable delay unit before entering power down mode through the DLL hold control signal. This preliminary fixation prevents voltage fluctuations during power down mode from affecting the DLL clock phase, thereby maintaining phase consistency and preventing lock failures.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The invention applies preliminary anti-action by using the DLL hold control signal to counteract the potential harmful effect of voltage fluctuations before they can cause phase differences. By fixing the delay time in advance, the system preemptively neutralizes the destabilizing influence of power down mode voltage variations on the DLL clock phase.

Inventive Principle:

Principle #9Preliminary anti-action

2Stability of the object's composition

If the delay time of the DLL variable delay unit is fixed before power down, then phase consistency is maintained, but the DLL cannot adapt to phase changes after power down

Engineering Contradiction:

ImproveDLL clock phase consistencyVSAvoidDLL phase adjustment capability

Core Design Contradiction:

Stability of the object's compositionVSAdaptability or versatility

Solution Approach 1:

The invention applies dynamics by making the delay time fixation conditional rather than permanent. The DLL hold control signal dynamically controls when to fix the delay time (during power down mode entry) and when to allow normal phase adjustment. This dynamic control allows the system to switch between stability and adaptability based on operational mode.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The invention applies continuity of useful action by ensuring that the DLL can continuously maintain phase consistency during power down mode while retaining the capability to continuously adjust phase when needed. The hold control signal enables continuous stable operation during critical periods without permanently disabling adaptation capabilities.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS7821308B2Delay locked loop and method of controlling the same

Publication Date: 2010.10.26 SK HYNIX INC

AI summary

A delay locked loop includes a DLL hold control unit that receives a first control signal and outputs a DLL hold control signal, and a DLL block that receives the DLL hold control signal and generates a DLL clock.