DLL Forward Clock Delay Measurement During Idle-Time Calibration

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Solution Overview

Problem

High-speed electronic devices face synchronization issues due to variations in manufacturing parameters and operating conditions, leading to clock delay inconsistencies, which affect performance and require calibration methods that disrupt normal operation by stopping the external clock signal.

Innovation Solution

A measure shot device is introduced to calibrate the DLL system in idle mode without discontinuing the external clock signal, using a calibration sequence to determine the forward clock path delay and adjust components accordingly, allowing partial operation during calibration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the external clock signal is stopped to perform calibration, then the calibration accuracy is improved, but the productivity is worsened due to operational disruption

Engineering Contradiction:
Improvecalibration accuracyVSAvoidoperational continuity
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The calibration process is segmented into two distinct modes: a calibration mode where the external clock is stopped for accurate delay measurement, and a normal operation mode where the clock runs continuously. This segmentation allows each mode to optimize for its specific purpose without compromising the other.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The calibration is performed as a preliminary action before normal operation begins, or during idle periods. The measure shot device captures the forward clock path delay characteristics in advance, so that subsequent operations can proceed without interruption while benefiting from the calibrated data.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the forward clock path delay is not calibrated, then the productivity is maintained, but the reliability is worsened due to synchronization issues

Engineering Contradiction:
Improveoperational continuityVSAvoidclock synchronization
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system performs self-calibration using its own internal resources. The measure shot device utilizes the existing clock tree, delay line, and phase detector to automatically measure and determine the forward clock path delay without requiring external calibration equipment or manual intervention, thereby maintaining both productivity and reliability.

Inventive Principle:
Principle #25Self-service

3Reliability

If a measure shot device is added to enable calibration during operation, then the device complexity is increased, but the reliability is improved through continuous synchronization

Engineering Contradiction:
Improveclock synchronizationVSAvoidsystem structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The measure shot device is designed to be multi-functional, serving both as a calibration instrument and as part of the normal clock distribution system. It leverages existing components like the delay line and phase detector for dual purposes: normal clock operation and forward clock path delay measurement, thereby minimizing the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The measure shot device acts as an intermediary that bridges the calibration function and the normal operation function. It interfaces with the existing clock tree and delay line structures, using them as mediators to perform delay measurement without requiring complete system redesign or adding complex external calibration equipment.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS7619453B2Delay-locked loop (DLL) system for determining forward clock path delay
Publication Date: 2009.11.17 MICRON TECHNOLOGY INC
  • US7619453B2 patent drawing
  • US7619453B2 patent drawing
  • US7619453B2 patent drawing

AI summary

A delayed locked loop (DLL) system and method for determining a forward clock path delay are disclosed. One embodiment of the DLL system includes a delay line having a plurality of delay stages. The DLL system also includes a measure shot device configured to determine a forward clock path delay of the DLL system. The measure shot device is configured to provide a calibration sequence into the DLL loop and to detect the calibration sequence after the calibration sequence has passed through the DLL loop. The measure shot device is further configured to count the number of clocks for a period of time between providing and detecting the calibration sequence. The number of clocks can be used to calibrate components of the DLL system.