DLL Circuit Inactive State for Memory Power Reduction
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Solution Overview
Problem
The power consumption of DLL circuits in memory devices increases significantly as memory device speed increases, affecting efficiency, as these circuits remain active during reading and standby states except for power-off mode.
Innovation Solution
A latency control circuit and method that allows the DLL circuit to enter an inactive state after locking the delay time, with the delay line circuit maintaining signal synchronization and delaying signals, reducing power consumption during reading and ODT operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the DLL circuit remains active during reading and standby operations to maintain signal synchronization, then signal timing accuracy is improved, but power consumption increases significantly
Solution Approach 1:
The DLL circuit's operational state is made dynamic, transitioning between active and inactive states based on operational requirements. The circuit is activated only when delay adjustment is needed and deactivated during stable operation periods, allowing the system to adapt its power consumption to actual needs while maintaining timing accuracy when required.
Solution Approach 2:
The DLL circuit operates periodically rather than continuously, being activated at specific intervals to adjust delay timing and then deactivated. This periodic activation maintains signal synchronization when necessary while significantly reducing average power consumption during standby and reading operations.
2Use of energy by moving object
If the DLL circuit is deactivated to reduce power consumption, then energy efficiency is improved, but signal synchronization capability is lost
Solution Approach 1:
The delay timing is adjusted in advance during active periods, and the adjusted timing parameters are maintained during inactive periods. This preliminary adjustment ensures that when the DLL circuit is reactivated, the signal synchronization is already optimized, eliminating the need for continuous adjustment and allowing safe deactivation.
Solution Approach 2:
The system monitors signal timing requirements and provides feedback to control the DLL circuit's activation. When timing drift is detected or operations requiring precise timing occur, the DLL circuit is activated to restore synchronization, ensuring reliability is maintained while minimizing power consumption during normal operation.
Data Source
AI summary
A latency control circuit and method are provided. The latency control circuit includes a DLL circuit, a latency counter circuit, a synchronization circuit, and a delay line circuit. The DLL circuit enters an inactive state after locking the delay time and provides an active signal at a disable state, delay locking information and loop delay information during the inactive state. The synchronization circuit stops providing a first clock signal according to the active signal at the disable state and then synchronously outputs an operation enabling signal and a second clock signal in response to an enablement of the operation signal. The delay line circuit receives the delay locking information, the operation enabling signal, and the second clock signal and outputs an operation delay signal and an output clock signal after the delay time.