Delay-Locked Loop Initialization Using Inherent Delay Measurement
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Solution Overview
Problem
Conventional delay locked loops (DLLs) in synchronous integrated circuits face challenges in achieving fast locking states and reducing excess circuitry, leading to increased size and power consumption, especially at higher clock frequencies, resulting in faulty data transfers and phase mismatches between internal and external clock signals.
Innovation Solution
The proposed DLL circuit employs a measure initialization mode with a feedback configuration that directly applies inherent delays to the coarse delay line during initialization, allowing for faster phase locking by minimizing additional delays and using a multiplexer to control the delay lines, thereby reducing the need for separate model delay circuits and excess logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional DLL circuits use separate model delay circuits and additional logic to compensate for inherent delays, then phase matching between internal and external clock signals can be achieved, but circuit size and power consumption increase
Solution Approach 1:
The patent extracts and eliminates the separate model delay circuit from the conventional DLL structure. Instead of using a duplicate model delay circuit to measure and compensate for inherent delays, the invention directly utilizes the inherent delay of the coarse delay line itself for phase matching, thereby removing unnecessary circuit components and reducing overall circuit size
Solution Approach 2:
The coarse delay line is made to serve dual functions: it acts as both the delay adjustment mechanism and the reference for measuring inherent delays. By using the same coarse delay line for both purposes rather than requiring a separate model delay circuit, the invention reduces circuit complexity while maintaining phase matching accuracy
2Measurement precision
If conventional DLL circuits use multiple additional delay lines and logic circuits for delay measurement and compensation, then clock synchronization can be achieved, but power consumption increases
Solution Approach 1:
The patent removes the power-consuming separate model delay circuit and associated measurement logic from the DLL structure. The inherent delay of the coarse delay line is directly utilized without requiring additional active measurement circuits, thereby significantly reducing power consumption while maintaining synchronization accuracy
Solution Approach 2:
The coarse delay line serves itself by providing its own inherent delay characteristics as the reference for phase matching. Instead of requiring external model delay circuits and control logic to measure and compensate for delays, the system uses the coarse delay line's own properties, eliminating the need for additional power-consuming measurement and compensation circuits
3Measurement precision
If conventional DLL circuits use complex delay measurement and compensation mechanisms, then phase lock can be achieved, but locking time increases
Solution Approach 1:
The patent applies preliminary action by directly pre-setting the coarse delay line to compensate for inherent delays during the initialization mode. Rather than requiring complex real-time measurement and iterative compensation during normal operation, the inherent delay is measured and compensated in advance, enabling faster phase locking when the DLL transitions to normal operation mode
Solution Approach 2:
The invention implements dynamic operation by having the DLL switch between two modes: initialization mode where inherent delays are measured and compensated by directly adjusting the coarse delay line, and normal operation mode where the pre-compensated delay is used. This dynamic switching between measurement and operation states reduces the time required to achieve phase lock compared to continuous complex measurement mechanisms
Data Source
AI summary
A clock generator having a delay locked loop and a delay control circuit. The delay locked loop receives an input clock signal and adjusts an adjustable delay circuit to generate an output clock signal that is synchronized with received input clock signal. The delay control circuit coupled to the delay locked loop generates a control signal to initialize the delay measure operation to adjust the adjustable delay circuit, after comparing the phase difference of the input clock signal and the output clock signal. The delay control circuit further generates a start measure control signal to start measuring a delay applied to the measurement signal propagating through the adjustable delay circuit, and generates a stop measure control signal to stop the delay measurement of the measurement signal. The delay adjustment of the delay locked loop is then adjusted to apply the delay measurement when synchronizing the input and output clock signals.