DLL Initialization Circuit to Prevent Harmonic Locking
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Solution Overview
Problem
Existing initialization circuits for delay locked loops (DLLs) often result in timing failures and harmonic locking due to initial delay values being significantly less than the reference clock signal period, and are unable to compensate for process-voltage-temperature (PVT) variations and frequency changes.
Innovation Solution
An initialization circuit comprising a sense circuit and a control circuit that adjusts the delay value of a DLL to equal a predetermined value for a duration, then increases it until it matches the reference clock signal period, incorporating a clock detection circuit to track PVT variations and changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the initial delay value is set significantly less than the reference clock signal period to initialize the DLL, then the DLL can start operation, but timing failure occurs in the phase detector
Solution Approach 1:
The initialization circuit performs preliminary action by setting the delay value to a predetermined value (less than the reference clock signal period) only for a predetermined time duration during startup. After this initial period, the delay value automatically increases to match the reference clock signal period, ensuring both successful startup and accurate phase detection operation.
2Speed
If the control signal voltage level is increased to increase the delay value, then the DLL can achieve larger delay, but harmonic locking or startup failure occurs
Solution Approach 1:
The initialization circuit applies preliminary action by temporarily setting the delay value to a predetermined value during the startup phase. This predetermined value is carefully selected to be less than the reference clock signal period, preventing harmonic locking while ensuring the DLL can start. After startup, the delay value naturally increases to the correct operating value without requiring excessive voltage increases.
3Device complexity
If the control signal is made independent and fixed, then the circuit design is simplified, but the DLL cannot compensate for PVT variations and frequency changes
Solution Approach 1:
The sense circuit implements feedback by continuously monitoring the relationship between the delayed clock signal and the reference clock signal. Based on this feedback, the control circuit dynamically adjusts the control signal to the loop filter, ensuring the delay value maintains the correct relationship with the reference clock signal period despite PVT variations or frequency changes, without requiring complex adaptive circuits.
Data Source
AI summary
An initialization circuit of a delay locked loop (DLL) includes a sense circuit and a control circuit. The sense circuit receives an enable signal, a reference clock signal, and various delayed reference clock signals, and outputs another enable signal. The control circuit receives the two enable signals and outputs and provides a control signal to a loop filter of the DLL to control a delay value associated with the DLL. The control signal is provided to the loop filter such that the delay value associated with the DLL equals a predetermined delay value for a predetermined time duration. Further, after a lapse of the predetermined time duration, the delay value associated with the DLL increases until a difference between a time period of the reference clock signal and the delay value equals a threshold value.