DLL Initialization Circuit Using Three Clock Phases for Trim Accuracy
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Solution Overview
Problem
The existing delay locked loop (DLL) initialization methods in SDRAMs are inefficient due to unawareness of Tac trim adjustments, leading to potential misalignment of input and output clocks, increased lock time, and power consumption, especially at higher clock speeds.
Innovation Solution
The improved DLL initialization circuitry uses three clock phases – the DLL reference clock, the reference clock trimmed by delay Tref, and the feedback clock trimmed by delay Tfb – to accurately measure and initialize the variable delay line, accounting for both positive and negative trim adjustments, thereby reducing post-initialization shifting and enhancing synchronization accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional two-phase initialization method is used, then circuit complexity is reduced, but measurement precision deteriorates due to unawareness of Tac trim adjustments
Solution Approach 1:
The initialization circuitry is segmented into three separate delay elements (first, second, and third delay elements) that process different clock phases independently. This segmentation allows each element to be optimized for specific measurement functions while collectively achieving Tac trim awareness, resolving the contradiction between circuit complexity and measurement precision.
Solution Approach 2:
A fourth delay element is introduced as an intermediary component that receives the output clock signal and provides a reference measurement. This intermediary element mediates between the three measurement phases and the final delay calculation, enabling accurate Tac trim compensation without significantly increasing overall circuit complexity.
2Reliability
If iterative adjustments are performed to achieve clock alignment, then synchronization accuracy is improved, but lock time increases
Solution Approach 1:
The initialization circuitry performs preliminary measurements using three different clock phases before the DLL enters normal operation. By pre-determining the optimal entry point into the variable delay line based on these measurements, the system eliminates the need for iterative adjustments during operation, thus achieving both high synchronization accuracy and fast lock time.
Solution Approach 2:
The measurement results from the three-phase initialization process provide feedback that directly determines the initial entry point configuration of the variable delay line. This feedback mechanism ensures accurate clock alignment from the start, preventing the need for time-consuming iterative adjustments and reducing overall lock time.
3Use of energy by moving object
If entry point is fixed at minimum delay, then power consumption is reduced, but synchronization accuracy deteriorates due to misalignment
Solution Approach 1:
Before normal operation begins, the initialization circuitry performs preliminary measurements to determine the optimal entry point into the variable delay line. This preliminary action ensures that the entry point is correctly configured for accurate synchronization, eliminating the need for continuous iterative adjustments that would increase power consumption during operation.
Solution Approach 2:
The entry point parameter of the variable delay line is dynamically configured based on measurement results from the three-phase initialization process. By changing the entry point parameter to the optimal position determined during initialization, the system achieves accurate clock alignment without requiring continuous power-intensive adjustments during normal operation.
Data Source
AI summary
Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay (e.g., entry point or exit point) by using three clock phases: the DLL reference clock (input to the delay line), the reference clock as trimmed by a delay Tref, and the feedback clock as trimmed by a delay Tfb. By using these three phases at the appropriate time, the measurement is aware of the Tac trim for both positive (Tref) and negative (Tfb) trims. Specifically, measurement ‘start’ and ‘stop’ signals each pass through only one of delays Tref and Tfb, such that error in the measurement is a function of both Tref and Tfb. This improves the accuracy of the measurement such that additional shifting of the DLL is not necessary after initialization, and allows a wide trim range even for high clock frequencies.