DLL Initialization Circuit Using Three Clock Phases for Fast Lock
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Solution Overview
Problem
The existing delay locked loop (DLL) initialization methods in SDRAMs are inefficient due to unawareness of Tac trim adjustments, leading to potential misalignment of input and output clocks, increased lock time, and power consumption, especially at higher clock speeds.
Innovation Solution
The improved DLL initialization circuitry uses three clock phases: the DLL reference clock, the reference clock trimmed by delay Tref, and the feedback clock trimmed by delay Tfb, allowing for accurate measurement and initialization aware of both positive and negative trims, reducing the need for post-initialization adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional DLL initialization methods are used, then the initialization process is simple, but measurement accuracy is poor and lock time increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing the relationship between Tac trim values and optimal entry points in a lookup table before operation. During initialization, the phase detector determines the required Tac trim adjustment, and the lookup table immediately provides the corresponding optimal entry point, eliminating the need for time-consuming iterative searches during actual operation.
Solution Approach 2:
The patent introduces a lookup table as an intermediary between the phase detector and the variable delay line entry point control. This lookup table mediates the relationship by storing pre-computed mappings from Tac trim requirements to optimal entry points, allowing the system to quickly translate phase detection results into precise delay line configuration without direct complex calculations.
2Adaptability or versatility
If Tac trim circuitry is added to adjust access time, then Tac compensation is achieved, but device complexity increases
Solution Approach 1:
The patent merges the Tac trim functionality with the existing DLL initialization and control mechanisms. Instead of adding completely separate trim circuitry, the invention integrates Tac compensation into the phase detection and entry point control system by using the phase detector's output to index into a lookup table that provides both Tac compensation and entry point optimization.
Solution Approach 2:
The lookup table serves multiple functions simultaneously: it provides Tac trim compensation, determines optimal entry points for the variable delay line, and enables fast initialization. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby limiting the increase in device complexity while achieving adaptability.
3Manufacturing precision
If entry point is varied to adjust delay, then delay control is achieved, but initialization becomes more complex
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing the relationship between Tac trim values and optimal entry points in a lookup table before operation. During initialization, the phase detector determines the required Tac trim adjustment, and the lookup table immediately provides the corresponding optimal entry point, eliminating the need for time-consuming iterative searches during actual operation.
Data Source
AI summary
Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay (e.g., entry point or exit point) by using three clock phases: the DLL reference clock (input to the delay line), the reference clock as trimmed by a delay Tref, and the feedback clock as trimmed by a delay Tfb. By using these three phases at the appropriate time, the measurement is aware of the Tac trim for both positive (Tref) and negative (Tfb) trims. Specifically, measurement ‘start’ and ‘stop’ signals each pass through only one of delays Tref and Tfb, such that error in the measurement is a function of both Tref and Tfb. This improves the accuracy of the measurement such that additional shifting of the DLL is not necessary after initialization, and allows a wide trim range even for high clock frequencies.