DLL Initial Delay Monitoring for Faster Clock Locking
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Solution Overview
Problem
Conventional DLL circuits face limitations in achieving fast locking times, which are essential for supporting high-speed operations in semiconductor integrated circuits due to the initial large phase difference between reference and feedback clock signals, leading to increased locking time.
Innovation Solution
Incorporating an initial delay monitoring unit to generate an initial setting code based on the phase difference between the reference and feedback clock signals, a shift register to produce a delay control code, and a delay line that delays the reference clock signal to minimize phase difference, thereby reducing the locking time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a conventional DLL circuit uses a shift register and delay line to perform delay locked operation, then the circuit structure is simple, but the locking time becomes long when initial phase difference is large
Solution Approach 1:
The patent applies preliminary action by measuring the initial phase difference between reference and feedback clock signals before the main delay locked loop operation begins. The initial delay monitoring unit captures phase information at power-up or reset, and the shift register pre-loads this measured value to establish an initial delay setting that is close to the target phase alignment. This preliminary measurement and pre-loading action significantly reduces the time required for the subsequent incremental delay adjustment, directly resolving the technical contradiction by minimizing locking time without requiring fundamental changes to the overall circuit structure.
2Reliability
If the delay control code changes by one bit for each loop period, then the circuit operation is stable, but the locking time increases when large phase difference exists
Solution Approach 1:
The patent resolves this contradiction by performing preliminary measurement of the initial phase difference and pre-loading the shift register with the measured value. This allows the delay control code to start from a value close to the final locked state, so that only minor incremental adjustments are needed during the normal loop operation. The stability of one-bit-per-loop changes is maintained throughout the locking process, but the total locking time is dramatically reduced because the starting point is already near the target, eliminating the need for many incremental steps.
3Speed
If the DLL circuit delays the reference clock signal by a predetermined time, then the phase of internal clock signal can be advanced, but the locking time increases due to large initial phase difference
Solution Approach 1:
The patent applies preliminary action by measuring the initial phase difference at the start of operation and using this measurement to pre-set the delay control code. This allows the delay line to immediately apply an appropriate delay to the reference clock signal that is close to the optimal value, rather than starting from zero or a fixed predetermined delay. The phase advancement is achieved rapidly because the initial delay setting is based on actual measured phase information, significantly reducing the time required to reach the locked state while maintaining the necessary phase advancement function.
Data Source
AI summary
A delay locked loop (DLL) circuit includes an initial operation setting unit configured to generate an initial operation signal in response to a reference clock signal and an operation start signal; a shift register configured to generate a delay control code in response to the initial operation signal, a phase comparison signal, and an initial setting code; a delay line configured to delay the reference clock signal or a feedback clock signal in response to the initial operation signal and the delay control code, thereby generating a plurality of unit delay clock signals; and an initial delay monitoring unit configured to generate the initial setting code in response to the reference clock signal and the plurality of unit delay clock signals.