DLL Initial Value Setting for Fast Locking
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Solution Overview
Problem
The Delay Locked Loop (DLL) in semiconductor devices experiences prolonged locking times as the frequency of the reference clock signal increases, leading to insufficient timing margin and reduced operation stability in semiconductor memory systems.
Innovation Solution
A semiconductor system that includes a controller and a semiconductor device with an initial value setting unit capable of selecting pre-stored code values for a delay control signal based on frequency information, allowing the DLL to set an optimal initial value for the delay control signal, thereby reducing locking time and enhancing operation timing margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frequency of the reference clock signal is increased, then the operation speed of the semiconductor device is improved, but the locking time of the DLL becomes considerably long
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing optimal delay control signal values in a lookup table before operation. When the DLL needs to lock at a specific frequency, the system directly retrieves the pre-computed initial value from the lookup table based on the target frequency, avoiding time-consuming real-time calculations and enabling fast locking even at high frequencies
2Speed
If the frequency of the reference clock signal is increased, then the operation speed is improved, but the operation stability is deteriorated
Solution Approach 1:
The system performs preliminary stability analysis and stores optimal delay control values that ensure stable operation at each frequency. By pre-determining these values through simulation or characterization, the system guarantees operation stability when retrieving values from the lookup table during actual high-frequency operation
Solution Approach 2:
The patent changes the parameter of delay control signal values based on frequency requirements. The lookup table stores different optimal delay control values for different frequency ranges, allowing the system to adapt parameters appropriately for each operating condition to maintain stability
3Speed
If the DLL performs locking operation at high frequency, then the operation speed is improved, but the timing margin becomes insufficient
Solution Approach 1:
The system performs preliminary optimization of delay control values to maximize timing margin at each frequency. The lookup table stores pre-calculated values that not only enable fast locking but also optimize the timing margin by accounting for process variations and environmental factors in advance
Data Source
AI summary
A semiconductor system includes: a controller suitable for outputting an external clock signal and a command/address signal; and a semiconductor device suitable for selecting one of pre-stored code values of a delay control signal to output an initial value control signal according to the command/address signal, and outputting an internal clock signal by delaying the external clock signal by a predetermined time based on the delay control signal having an initial value that is set in response to the initial value control signal.