Delay Locked Loop Initialization for Faster Multi-Frequency Locking
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Solution Overview
Problem
Conventional DLL circuits in semiconductor devices do not efficiently adjust clock signals to desired phases across various frequencies during initial setting operations, leading to slow locking times and reduced versatility.
Innovation Solution
A semiconductor device with a DLL circuit that includes a delay unit, phase comparator circuit, counter circuit, and initial delay amount control circuit, where the initial delay amount is determined based on the cycle of the clock signal, allowing for faster adjustment across different frequencies by varying the delay amount accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a conventional DLL circuit uses fixed delay adjustment range for all frequencies, then the circuit structure remains simple, but the locking time becomes excessively long for low frequencies and the adjustment is inefficient
Solution Approach 1:
The delay adjustment range is made dynamic by detecting the clock signal frequency and selecting different initial delay amounts accordingly. The initial delay amount control circuit adjusts the starting delay value based on whether the clock frequency is high or low, enabling efficient convergence to the locked state across different frequency ranges without requiring a uniformly large adjustment range that would complicate the circuit.
Solution Approach 2:
The initial delay amount parameter is changed based on the detected clock frequency. When a high frequency is detected, a first (smaller) initial delay amount is set, while when a low frequency is detected, a second (larger) initial delay amount is set. This parameter adaptation allows the DLL to optimize its locking behavior for different operating conditions without increasing structural complexity.
2Adaptability or versatility
If the DLL circuit uses a large delay adjustment range to cover all frequencies, then it can handle various frequencies, but the locking time increases significantly for high frequency signals
Solution Approach 1:
The circuit dynamically adapts its delay adjustment characteristics based on the input clock frequency. By detecting whether the frequency is high or low, the system selects appropriate initial delay amounts, thereby optimizing the locking speed for each frequency range while maintaining the ability to handle a wide variety of frequencies.
Solution Approach 2:
Different initial delay amounts are applied locally to different frequency ranges. High frequency signals receive a smaller initial delay amount (first initial delay amount), while low frequency signals receive a larger initial delay amount (second initial delay amount). This localized optimization ensures that each frequency range receives the appropriate delay adjustment without affecting other frequency ranges.
3Loss of time
If the DLL circuit uses a small delay adjustment range for high frequencies, then the locking speed is fast, but the circuit cannot properly handle low frequency signals
Solution Approach 1:
The initial delay amount parameter is selectively changed based on the detected clock frequency. The initial delay amount control circuit detects whether the input clock has high or low frequency and accordingly sets either the first initial delay amount (for high frequency) or the second initial delay amount (for low frequency), enabling the circuit to optimize locking speed for high frequencies while maintaining proper handling of low frequencies.
Solution Approach 2:
The delay adjustment characteristics are made dynamic by frequency detection. The circuit transitions between different initial delay amount settings based on the operating frequency, allowing it to achieve fast locking for high frequencies while retaining the capability to properly adjust delays for low frequency signals.
Data Source
AI summary
A method for initializing a delay locked loop having a delay circuit includes a plurality of serially connected delay elements and a counter circuit for selecting an output of one of the delay elements as an output clock signal. The method includes resetting an initial delay control circuit, generating, with the initial delay control circuit, a pulse based on a period of an input clock signal, determining, with the initial delay control circuit, a number of delay elements required to produce a delay time at least substantially equivalent to a pulse width for a preset signal, initializing the counter circuit based on the preset signal and adjusting the counter circuit in response to phases of the input and output clock signals.