DLL Phase Detector Input Delays for Selective Clock Skew
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Solution Overview
Problem
Conventional delay-locked loop (DLL) architectures in integrated circuits (ICs) indiscriminately correct for all types of clock skew, including both useful and non-useful skews, which can limit chip frequency improvements by uniformly compensating for skew between critical and non-critical paths.
Innovation Solution
Incorporating programmable delay elements at the phase detector inputs of a DLL to introduce a controllable skew between clocks, which cannot be corrected by the DLL, allowing for selective improvement of chip frequency by adjusting latency of critical paths at the expense of non-critical paths, thereby offsetting systematic skew due to clock distribution differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DLL architectures indiscriminately correct for all types of clock skew, then static and dynamic skews are compensated, but chip frequency is limited due to uniform compensation across critical and non-critical paths
Solution Approach 1:
The patent applies local quality by introducing programmable delay elements at specific phase detector inputs to create selective skew adjustment. Instead of uniform skew correction across all paths, the invention allows different delay adjustments for critical paths versus non-critical paths. The programmable delay elements enable localized skew modification at the phase detector input stage, permitting critical paths to receive optimized skew compensation while non-critical paths maintain their original timing characteristics, thus resolving the contradiction between reliable skew compensation and maximum chip frequency.
2Productivity
If programmable delay elements are added at phase detector inputs to introduce controllable skew, then chip frequency is improved by optimizing critical paths, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the clock distribution system into distinct segments: fixed delay elements for static skew compensation, variable delay elements for dynamic skew adjustment, and programmable delay elements at phase detector inputs for selective path optimization. This segmentation allows each delay mechanism to operate independently with specific functions, enabling frequency improvement through targeted skew control while maintaining modular architecture that limits overall system complexity.
Solution Approach 2:
The patent applies dynamics by implementing multiple levels of delay control: static fixed delays for baseline compensation, dynamically adjustable variable delays for real-time skew correction, and programmable delays for selective path optimization. The programmable delay elements can be configured through control signals to introduce specific skew amounts, enabling adaptive frequency optimization without permanently altering the DLL architecture, thus improving productivity while keeping device complexity manageable through flexible, reconfigurable control.
Data Source
AI summary
A delay-locked loop (DLL) and corresponding method improve frequency of a chip. The DLL comprises a first programmable delay element configured to output a first clock, a second programmable delay element configured to output a second clock a phase detector. The phase detector includes a first clock input and a second clock input. The first and second programmable delay elements are further configured, in combination, to introduce a controllable skew between the first and second clocks. The DLL is configured to input the first and second clocks to the first and second clock inputs of the phase detector, respectively. The controllable skew is configured to improve the frequency of the chip.