DLL Inverter Circuit Layout for Stable Clock Phase Adjustment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The fine adjustment section of synchronous memory DLL circuits experiences phase adjustment accuracy fluctuations due to uneven current flow when all clocked inverters are turned off, leading to difficulty in accurately controlling the phase of the output clock signal.
Innovation Solution
The semiconductor device incorporates a configuration where additional inverters without control nodes output signals alongside clocked inverter circuits, allowing for precise control of signal output and phase adjustment by ensuring consistent current flow, thereby stabilizing phase adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If all clocked inverters are turned off based on delay adjustment control signals, then phase adjustment range is improved, but phase adjustment accuracy fluctuates due to uneven current flow
Solution Approach 1:
The patent introduces additional inverters without control nodes that operate continuously to provide a baseline current flow. This ensures homogeneous current distribution through the delay line regardless of the state of clocked inverters, preventing the uneven current flow that causes phase accuracy fluctuations when clocked inverters are turned off.
Solution Approach 2:
The additional inverters act as intermediary elements between the clocked inverters and the delay line. They maintain continuous operation to provide a stabilizing current path, mediating the effect of clocked inverter shutdown on the overall current distribution and phase adjustment accuracy.
2Adaptability or versatility
If clocked inverters are selectively turned on or off to control delay amount, then phase adjustment flexibility is improved, but current flow uniformity deteriorates causing phase fluctuations
Solution Approach 1:
By adding inverters without control nodes that operate continuously, the patent creates a homogeneous current flow foundation. This baseline current distribution remains uniform regardless of which clocked inverters are active, maintaining current flow uniformity while allowing flexible phase adjustment through clocked inverter control.
Solution Approach 2:
The additional inverters provide a pre-established current path that cushions against the disruptions caused by turning clocked inverters on or off. This prior cushioning ensures that current flow uniformity is maintained even when clocked inverters change state, preventing phase fluctuations.
3Device complexity
If all clocked inverters accept the same control signals, then circuit complexity is reduced, but phase control precision deteriorates due to inability to independently control current distribution
Solution Approach 1:
The patent segments the inverter population into two functional groups: clocked inverters with control nodes for phase adjustment, and additional inverters without control nodes for current stabilization. This segmentation allows independent optimization of each group's function, achieving precise phase control while maintaining simple control signal architecture.
Solution Approach 2:
The additional inverters without control nodes serve a universal stabilizing function across all phase adjustment conditions. They provide continuous current flow that benefits all phase adjustment operations, enabling precise phase control without requiring complex control signals for each inverter.
Data Source
AI summary
A semiconductor device includes a first input terminal configured to receive a first clock signal, first control terminals configured to receive first control signals respectively, an output terminal, first inverters each including an input node coupled to the first input terminal, a control node coupled to a corresponding one of the first control terminals and an output node coupled to the output terminal, each of the first inverters being configured to be controlled to output an inverted first clock signal to the output terminal in response to a corresponding one of the first control signals supplied to a corresponding one of the control nodes, and an additional first inverter including an input node coupled to the first input terminal and an output node coupled to the output terminal, the additional first inverter being free from any other control nodes to output an inverted first clock signal to the output terminal.