DLL Clock Synchronization Circuit for Jitter-Aware Phase Locking
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Solution Overview
Problem
Conventional delay locked loop (DLL) circuits in semiconductor devices face issues with synchronization when jitter occurs, leading to failure in delay locking operations due to continuous coarse mode operation and limited delay amount, resulting in unsynchronized phases of internal and external clocks.
Innovation Solution
A semiconductor device with a DLL circuit that includes phase detectors and a phase difference detection signal generator capable of detecting jitter and adjusting the phase synchronization operation, allowing the circuit to switch between coarse and fine modes based on detected phase differences, ensuring accurate synchronization of clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the DLL circuit operates in coarse mode continuously due to jitter detection failure, then the phase synchronization capability deteriorates, but the delay amount is limited and cannot achieve accurate clock synchronization
Solution Approach 1:
The phase detection function is segmented into three separate phase detectors (first, second, and third phase detectors), each responsible for detecting different phase relationship scenarios. This segmentation allows the system to accurately detect jitter conditions and distinguish them from genuine phase differences, preventing continuous coarse mode operation while maintaining reliable delay locking.
2Measurement precision
If the phase detector cannot distinguish jitter from phase difference, then the synchronization accuracy deteriorates, but adding complex detection logic increases circuit complexity
Solution Approach 1:
Each phase detector is designed with specialized local functionality to detect specific phase relationship patterns. The first phase detector compares the first clock with the second clock, the second phase detector compares the first clock with the delayed second clock, and the third phase detector compares the delayed first clock with the second clock. This local specialization enables accurate jitter discrimination without requiring complex centralized logic.
3Productivity
If the delay amount is limited due to continuous coarse mode operation, then the clock synchronization capability deteriorates, but switching to fine mode prematurely causes synchronization failure
Solution Approach 1:
The DLL circuit dynamically switches between coarse mode and fine mode based on real-time phase detection results. The three phase detectors continuously monitor phase relationships and provide feedback to the delay controller, which adjusts the delay amount accordingly. This dynamic adaptation allows the system to achieve fast initial synchronization through coarse mode while transitioning to precise fine mode when appropriate, optimizing both synchronization speed and precision.
Data Source
AI summary
A semiconductor device includes a first phase detector for detecting a phase of a second clock by comparing the phase of the second clock with the phase of the first clock, a second phase detector for detecting a phase of a clock obtained by delaying the second clock by a set delay amount, a third phase detector for detecting the phase of the second clock by delaying the first clock by the set delay amount, and a phase difference detection signal generator for setting a logic level of a phase difference detection signal corresponding to a phase difference between the first and second clocks detecting that the phase of the first or second clock is changed, and change the logic level of the phase difference detection signal.