DLL-Based Data Latch Timing Adjustment for NAND Flash Reads
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Solution Overview
Problem
As NAND flash memory data transfer speeds increase, the valid period for latching read data becomes shorter, making it difficult to set and maintain a suitable delay for the data latch signal, leading to potential failures in reading data due to temperature and voltage fluctuations.
Innovation Solution
A storage device configuration that includes a DLL circuit, a latch circuit, and a delay amount adjustment circuit, which adjusts the delay of the clock signal based on latch results to ensure accurate data read timing, using a delay amount optimization method that determines the appropriate delay value by checking data match with reference data and adjusting the DLL's delay accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fixed delay amount is preset to the data latch signal, then the data can be latched at the correct timing under nominal conditions, but the delay time changes due to temperature and voltage fluctuations causing read data to fail within the valid period
Solution Approach 1:
The patent applies dynamics by making the delay amount adjustable rather than fixed. The delay element's delay time is dynamically modified based on detection results, allowing the system to adapt to temperature and voltage fluctuations. This transforms a static delay configuration into a dynamic one that can respond to environmental changes, resolving the contradiction between initial timing precision and ongoing reliability.
Solution Approach 2:
The patent implements feedback by detecting whether read data is correctly latched and using this information to adjust the delay amount. The delay amount modification unit receives feedback about latch success and automatically modifies the delay element's parameters accordingly. This closed-loop feedback mechanism ensures that the system maintains reliable data reading despite environmental variations.
2Productivity
If the data transfer speed of NAND memory is increased, then faster data read performance is achieved, but the valid period for latching read data becomes shorter making it difficult to preset appropriate delay
Solution Approach 1:
The patent makes the delay amount dynamically adjustable to match the increased data transfer speed. Rather than using a fixed delay preset during manufacturing, the system can modify the delay element's parameters in operation. This dynamic adjustment capability allows the system to maintain precise latch timing even as data transfer speeds increase and valid periods shorten.
Solution Approach 2:
The patent changes the delay parameter based on detection results and operating conditions. The delay amount modification unit adjusts the delay element's delay time parameter to optimize latch timing for the current data transfer speed. This parameter change approach allows the system to adapt to faster transfer rates without sacrificing latch precision.
3Device complexity
If a delay element with fixed preset delay is used, then the device complexity is reduced, but the system cannot adapt to temperature and voltage fluctuations affecting latch timing
Solution Approach 1:
The patent introduces dynamic adjustability to the delay element while maintaining relatively simple overall device complexity. The delay amount modification unit provides the necessary adaptability through automated parameter adjustment based on detection feedback. This dynamic component allows environmental adaptation without requiring complex manual adjustment mechanisms or multiple fixed delay circuits.
Solution Approach 2:
The patent implements self-service by enabling the delay element to automatically adjust its own parameters based on detection results. The delay amount modification unit allows the system to self-correct timing issues without external intervention. This self-adjusting capability provides environmental adaptability while keeping the device structure relatively simple, as the system manages its own optimization.
Data Source
AI summary
According to one embodiment, a storage device includes a storage medium, a DLL circuit, a latch circuit, and a delay amount adjustment circuit. The DLL circuit gives a predetermined amount of delay to an inputted clock signal, the latch circuit latches data outputted from the storage medium in accordance with the clock signal delayed in the DLL circuit, the delay amount adjustment circuit adjusts the delay amount that the DLL circuit is to give to the clock signal based on a latch result by the latch circuit.