Clock Recovery Circuit Prediction for DLL Latency and Jitter
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Solution Overview
Problem
Conventional clock recovery circuits using delay-locked loops (DLLs) suffer from latency issues, leading to jitter amplification at high frequencies due to the latency between phase error detection and phase shift application, resulting in an undesirable frequency-domain observed jitter transfer function (OJTF) peaking.
Innovation Solution
Incorporating a predictor and a delay line in the clock recovery circuit to adjust the delay of the phase-adjusted clock, allowing immediate compensation for phase errors by predicting future changes in the phase control signal, thereby reducing latency and eliminating OJTF peaking at high jitter frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the DSP operates at a lower frequency for ease of implementation, then the device complexity is reduced, but the latency in the DLL increases
Solution Approach 1:
The patent applies preliminary action by predicting future phase errors based on current and past phase error signals. The predictor generates anticipated phase error values in advance, allowing the system to compensate for latency by pre-calculating correction values that will be needed in the future, thus reducing the effective latency impact while maintaining low DSP operating frequency
2Ease of operation
If the DSP operates at a lower frequency, then the ease of operation is improved, but the jitter suppression performance deteriorates at high frequencies
Solution Approach 1:
The predictor performs preliminary calculation of future phase errors, enabling the low-frequency DSP to maintain high-frequency jitter suppression performance. By anticipating future phase error conditions, the system can apply appropriate corrections without requiring the DSP to operate at high frequencies, thus maintaining both ease of implementation and reliability
3Device complexity
If latency in the DLL is present, then the device complexity remains manageable, but the OJTF exhibits peaking at high frequencies
Solution Approach 1:
The predictor calculates anticipated phase errors in advance, allowing the system to compensate for latency-induced phase misalignment. This preliminary calculation enables precise phase alignment to be maintained despite the presence of DLL latency, preventing OJTF peaking while keeping device complexity manageable
Solution Approach 2:
The system uses feedback by continuously monitoring phase error signals and using them to update predictions. The predictor utilizes current and past phase error measurements to generate accurate predictions of future phase errors, creating a feedback mechanism that maintains phase alignment precision despite latency
Data Source
AI summary
A clock recovery circuit includes a phase detector, a loop filter, a phase rotator, a predictor and a delay line. The phase detector receives an input data signal and generates a phase error signal for estimating phase error in the input data signal when referred to a recovered clock. The loop filter receives the phase error signal and determines a phase control signal based on the phase error signal. The phase rotator receives the phase control signal, and provides a phase adjusted clock based on a reference clock and the phase control signal. The predictor receives the phase error signal, and determines a delay control signal based on the phase error signal. The delay line outputs the recovered clock by delaying the phase adjusted clock from the phase rotator using the delay control signal from the predictor, and provides the recovered clock to the phase detector.