DLL Dual Locking Point Latency Control for Voltage Variation
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Solution Overview
Problem
Semiconductor circuits face challenges in controlling latency, particularly CAS latency and data output path delay, which are affected by power supply voltage variations, leading to inconsistent performance.
Innovation Solution
A latency control circuit and method utilizing a delay locked loop (DLL) with dual locking points to generate a DLL clock signal and adjust latency, including a control unit to generate latency control signals based on reset and delay signals, and a latency signal generation unit to adjust command signals, ensuring precise latency control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a delay locked loop (DLL) is used to compensate delay time in a data output path, then data output latency can be controlled, but the delay characteristics change according to power supply voltage variations
Solution Approach 1:
The patent changes the operating parameters of the DLL by introducing dual locking points (first and second locking points) with different delay amounts. The control unit dynamically selects between these locking points based on power supply voltage conditions, thereby adapting the delay characteristics to compensate for voltage variations and maintain stable latency control.
Solution Approach 2:
The system dynamically switches between different DLL operating modes (first locking point and second locking point) based on real-time power supply voltage conditions. This dynamic adaptation allows the DLL to maintain optimal delay characteristics across varying voltage conditions, resolving the contradiction between latency precision and delay stability.
2Speed
If CAS latency is controlled in a data read operation, then read speed can be optimized, but data output path delay variations affect overall latency accuracy
Solution Approach 1:
The control unit monitors power supply voltage conditions and uses this feedback to dynamically select the appropriate DLL locking point. This feedback mechanism ensures that the total latency (CAS latency plus data output path delay) remains accurate by compensating for voltage-induced delay variations in real-time, while maintaining optimized read speed.
3Device complexity
If a single locking point is used in DLL, then circuit complexity is reduced, but latency control cannot compensate for power supply voltage variations
Solution Approach 1:
The system implements a dynamic DLL structure with dual locking points that can switch between different delay characteristics based on power supply voltage conditions. This dynamic approach maintains reliability under varying voltage conditions while keeping the circuit structure manageable through systematic design.
Solution Approach 2:
The patent introduces multiple locking points with different delay parameters to the DLL structure. By changing the delay parameters based on voltage conditions, the system achieves reliable latency control without requiring overly complex circuitry, as the parameter changes are implemented through controlled switching rather than complete structural redesign.
Data Source
AI summary
A latency control circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a clock signal by a delay time varied according to any one of dual locking points, and generate a loop change signal according to a locking point change; a control unit configured to generate a latency control signal in response to a reset signal, a delay signal generated by delaying the reset signal by a first delay time, and the loop change signal; and a latency signal generation unit configured to adjust a latency of a command signal in response to the latency control signal and output a latency signal.