DLL Lock Detector Using Analog Charge Control Against PVT Noise
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Solution Overview
Problem
Conventional lock detectors for delay-locked loops (DLLs) are prone to noise and malfunctions due to environmental variations, leading to incorrect lock state determination and reduced reliability, and they increase the size and power consumption of the DLL.
Innovation Solution
A lock detector using analog charging and discharging operations based on multiple delay signals from a voltage-controlled delay line, with a lock detection unit generating a charge control signal to control currents and detect the lock state, and a bias unit providing a bias voltage to manage the charge current, while being insensitive to noise through a Schmitt trigger circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a digital logic type lock detector is used to detect the lock state of the DLL, then the lock state can be determined, but the detector is influenced by environmental variations (PVT) causing noise and malfunctions, reducing reliability
Solution Approach 1:
The patent replaces the digital logic type lock detector with an analog type lock detector that uses continuous voltage signals instead of discrete logic levels. The analog detector compares the voltage level of a node with a reference voltage to determine lock state, making it insensitive to environmental variations such as process, voltage, and temperature changes that affect digital logic components.
Solution Approach 2:
The patent changes the detection parameter from digital logic levels to analog voltage levels. By monitoring the voltage level at a specific node and comparing it with a reference voltage, the system can accurately detect lock state without being affected by PVT variations that cause noise in digital logic circuits.
2Reliability
If many logic components are used in the lock detector, then the lock state can be detected, but the size of the DLL increases and power consumption increases
Solution Approach 1:
The patent extracts and eliminates unnecessary logic components from the lock detector circuit. By using a simplified analog detection method that only requires voltage level comparison instead of multiple logic gates, the circuit size is reduced while maintaining accurate lock state detection capability.
Solution Approach 2:
The patent substitutes complex digital logic components with a simpler analog voltage comparison mechanism. This replacement dramatically reduces the number of components needed in the lock detector while preserving the ability to accurately determine lock state.
3Reliability
If many logic components are used in the lock detector, then the lock state can be detected, but the power consumption for driving the circuit increases
Solution Approach 1:
The patent removes excessive logic components from the detector circuit, thereby reducing the total power consumption. The analog voltage comparison approach requires significantly fewer active components than a digital logic implementation, leading to lower overall power usage while maintaining detection accuracy.
Solution Approach 2:
The patent replaces power-hungry digital logic components with a low-power analog voltage comparison circuit. This substitution reduces the dynamic power consumption associated with switching logic gates while maintaining the lock state detection function.
Data Source
AI summary
A lock detector of a delay-locked loop (DLL) includes a lock detection unit and a bias unit. The lock detection unit generates a charge control signal based on a reference current received from an external source and a plurality of delay signals received from an external voltage-controlled delay line (VCDL), controls a charge current based on the charge control signal, and detects a lock state of the DLL based on a voltage that varies depending on the charge current. The bias unit provides a bias voltage for controlling a magnitude of the charge current. Therefore, the lock detector stably detects a lock state of the DLL.


