DLL Lock Failure Detection With Duty Cycle Correction
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Solution Overview
Problem
Conventional self bias DLLs experience lock failures due to distortion of the duty cycle, which results in insufficient charge-up time and failure to lock the internal clock signal to the external clock signal, especially when the RC time constant of delay cells is increased to enhance delay.
Innovation Solution
An apparatus comprising a lock failure detector, a duty cycle correction unit, and a delay unit that detects lock failures and corrects duty cycle distortions by generating a lock failure signal to adjust the duty cycle, ensuring the internal clock signal is properly synchronized with the external clock signal, using a differential amplifying circuit and charge pump to amplify and correct the duty cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the RC time constant of delay cells is increased to increase delay, then the delay capability is improved, but the capacitor charge-up time increases causing lock failure
Solution Approach 1:
The duty cycle correction circuit performs preliminary action by correcting the duty cycle of the external clock signal before it enters the delay line. This ensures that the delay cells receive a properly timed clock signal with sufficient high-level duration, allowing capacitors to charge adequately even with increased RC time constants, thus preventing lock failure while maintaining enhanced delay capability
Solution Approach 2:
The invention changes the parameter of duty cycle by detecting lock failure conditions and automatically adjusting the duty cycle of the external clock signal through the duty cycle correction circuit. This parameter change ensures optimal charging time for capacitors in delay cells with increased RC time constants, resolving the contradiction between enhanced delay and sufficient charge-up time
2Speed
If the RC time constant is increased to enhance delay, then the delay performance is improved, but lock failure occurs due to insufficient charge-up time
Solution Approach 1:
The invention implements feedback by using a lock failure detector to monitor whether the internal clock signal is properly locked to the external clock signal. When lock failure is detected, the system activates the duty cycle correction circuit to adjust the clock signal parameters, creating a closed-loop control that maintains reliable locking despite increased RC time constants and enhanced delay performance
Solution Approach 2:
The duty cycle correction circuit performs preliminary correction of the external clock signal before it reaches the delay line, ensuring that capacitors have sufficient charge-up time even when RC time constants are increased. This preliminary action prevents lock failure and maintains reliability while preserving the improved delay performance
Data Source
AI summary
An apparatus for detecting a lock failure and correcting a duty cycle includes a lock failure detector configured to determine whether a first internal clock signal is locked to a second internal clock signal and to output a lock failure signal in response thereto, a duty cycle correction unit configured to correct a duty cycle of an external clock signal responsive to the lock failure signal and to output the duty-cycle-corrected external clock signal as the first internal clock signal, and a delay unit configured to generate the second internal clock signal by delaying the first internal clock signal.