DLL Lock Detection Circuit for Stable PWM Signal Synchronization
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Solution Overview
Problem
The initial state operation of DLL circuits in signal transfer devices, such as photocouplers, is unstable due to difficulties in synchronizing multi-phase clock signals with a reference clock signal, leading to challenges in maintaining stable lock detection and demodulation of PWM signals.
Innovation Solution
A lock detection circuit is integrated into the DLL circuit, comprising a reference clock signal generation, delay circuit, phase comparison circuit, and charge pump, which generates control signals to adjust the delay amount of the multi-phase clock signals within specific thresholds, ensuring stable operation by controlling the delay lines to maintain the delay amount within the operable range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the DLL circuit operates in the initial state without input signals, then the circuit structure remains simple, but the operation becomes unstable due to difficulty in synchronizing multi-phase clock signals with reference clock signal
Solution Approach 1:
The patent applies preliminary action by detecting the initial state before normal operation begins and pre-setting the delay amount of the delay circuit to a specific value. This preliminary configuration ensures that when the input signal is applied, the multi-phase clock signals are already close to the correct phase relationship with the reference clock signal, enabling stable operation from the start without requiring complex additional circuitry.
2Device complexity
If the delay amount of multi-phase clock signals is not controlled within specific thresholds, then the device complexity is reduced, but the lock detection reliability deteriorates
Solution Approach 1:
The patent implements feedback by continuously monitoring the phase relationship between multi-phase clock signals and the reference clock signal through the phase comparison circuit. When the delay amount falls outside specific thresholds, the feedback mechanism triggers adjustment of the delay circuit to bring the delay amount back within the acceptable range, ensuring accurate lock detection while maintaining manageable device complexity through automated control.
3Ease of operation
If the phase synchronization is not maintained within specific thresholds, then the ease of operation is improved, but the demodulation precision of PWM signals deteriorates
Solution Approach 1:
The patent applies dynamics by making the delay amount adjustable and controllable rather than fixed. The delay circuit can dynamically change its delay characteristic based on feedback from the phase comparison circuit, allowing the system to automatically maintain optimal phase synchronization between multi-phase clock signals and reference clock signal. This dynamic adjustment ensures precise PWM demodulation while keeping the operation straightforward through automated control.
Data Source
AI summary
According to one embodiment, a lock detection circuit includes an initial state response circuit. The initial state response circuit is configured to output a third control signal to delay lines and cause a charge pump to stop an output of a second control signal when a pulse width modulation signal is not input, the third control signal is configured to control a delay amount to cause a delay amount of an entire delay circuit to be within one selected from a range in which an OVER signal generation circuit is operable, a range in which an UNDER signal generation circuit is operable, and a range that is greater than an UNDER threshold and less than an OVER threshold.