DLL Locking Control for Memory Gear Down Mode Latency
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Solution Overview
Problem
Memory devices, such as DDR4, face challenges in maintaining a locked delay locked loop (DLL) and adjusting latency when transitioning to a gear down mode, which affects power consumption and timing constraints, due to changes in internal clock frequency.
Innovation Solution
Implementing DLL locking control and CAS latency control mechanisms that adjust the loop counter value and latency based on whether the loop delay is even or odd, ensuring the DLL remains locked and latency is maintained by inverting the feedback signal when necessary, and adjusting the clock rate and latency values accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the internal clock rate is reduced in gear down mode, then power consumption is reduced and timing constraints are relaxed, but the DLL may lose lock and latency cannot be properly adjusted
Solution Approach 1:
The patent applies preliminary action by detecting the loop delay characteristic (even or odd number of clock cycles) before the gear down transition occurs. Based on this detection, the system pre-configures the appropriate feedback path (either direct or inverted) to ensure the DLL maintains proper locking behavior during the clock frequency transition, preventing lock loss before it can occur
Solution Approach 2:
The patent implements dynamics by making the feedback path configuration dynamic rather than fixed. The system can switch between two feedback configurations (direct feedback for even loop delays, inverted feedback for odd loop delays) depending on the detected loop delay characteristic. This dynamic reconfiguration allows the DLL to adapt to different operating conditions and maintain stability during gear down transitions
2Use of energy by moving object
If the internal clock rate is reduced in gear down mode, then power consumption is reduced and timing constraints are relaxed, but latency of the forward path cannot be properly adjusted
Solution Approach 1:
The patent uses feedback by continuously monitoring the loop delay characteristic of the DLL and using this information to control the feedback path configuration and latency adjustment. The system detects whether the loop delay is even or odd, and based on this feedback, automatically selects the appropriate configuration to maintain proper timing relationships during gear down mode
Solution Approach 2:
The system applies self-service by automatically detecting its own loop delay characteristic and self-adjusting the feedback path configuration and latency settings without external intervention. The DLL monitoring circuit autonomously determines the appropriate configuration and applies the necessary adjustments, enabling the system to adapt to gear down mode independently
3Reliability
If the feedback signal is inverted based on loop delay detection, then the DLL remains locked during gear down mode, but the system complexity increases due to additional control mechanisms
Solution Approach 1:
The patent merges the loop delay detection function with the existing DLL control logic. The same circuitry that monitors DLL operation is used to detect the loop delay characteristic (even or odd), and this detection is integrated with the existing feedback path selection mechanism. By combining these functions, the patent avoids adding completely separate control circuits, thereby reducing the increase in system complexity
Data Source
AI summary
Apparatuses and methods for controlling timing circuit locking and/or latency during a change in clock frequency (e.g. gear down mode) are described herein. An example apparatus may include a timing circuit. The timing circuit may be configured to provide a clock signal to the forward path, adjust a rate of the clock signal responsive to receipt of a command to adjust the rate of the clock signal, select a feedback clock signal responsive to a loop delay of the timing circuit, and provide a control signal to an adjustable delay circuit of the forward path circuit. Another example apparatus may include a forward path configured to delay a signal based at least in part on a loop delay and a latency value, and a latency control circuit configured to provide an adjusted latency value as the latency value responsive to receipt of a command, wherein the forward path is configured to operate at least in part at an adjusted clock rate responsive to receipt of the command.